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arm64: dts: lx2160a: Correct CPU core idle state name

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lx2160a support PW15 but not PW20, correct name to avoid confusing.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Fixes: 00c5ce8ac0 ("arm64: dts: lx2160a: add cpu idle support")
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Ran Wang
2019-09-17 15:33:56 +08:00
committed by Shawn Guo
parent 21094ba5c1
commit 07159f67c7
1 changed files with 18 additions and 18 deletions
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36
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
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@@ -33,7 +33,7 @@
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>; next-level-cache = <&cluster0_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@1 { cpu@1 {
@@ -49,7 +49,7 @@
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>; next-level-cache = <&cluster0_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@100 { cpu@100 {
@@ -65,7 +65,7 @@
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>; next-level-cache = <&cluster1_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@101 { cpu@101 {
@@ -81,7 +81,7 @@
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>; next-level-cache = <&cluster1_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@200 { cpu@200 {
@@ -97,7 +97,7 @@
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>; next-level-cache = <&cluster2_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@201 { cpu@201 {
@@ -113,7 +113,7 @@
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>; next-level-cache = <&cluster2_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@300 { cpu@300 {
@@ -129,7 +129,7 @@
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>; next-level-cache = <&cluster3_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@301 { cpu@301 {
@@ -145,7 +145,7 @@
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>; next-level-cache = <&cluster3_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@400 { cpu@400 {
@@ -161,7 +161,7 @@
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>; next-level-cache = <&cluster4_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@401 { cpu@401 {
@@ -177,7 +177,7 @@
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>; next-level-cache = <&cluster4_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@500 { cpu@500 {
@@ -193,7 +193,7 @@
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>; next-level-cache = <&cluster5_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@501 { cpu@501 {
@@ -209,7 +209,7 @@
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>; next-level-cache = <&cluster5_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@600 { cpu@600 {
@@ -225,7 +225,7 @@
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>; next-level-cache = <&cluster6_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@601 { cpu@601 {
@@ -241,7 +241,7 @@
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>; next-level-cache = <&cluster6_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@700 { cpu@700 {
@@ -257,7 +257,7 @@
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>; next-level-cache = <&cluster7_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@701 { cpu@701 {
@@ -273,7 +273,7 @@
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>; next-level-cache = <&cluster7_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cluster0_l2: l2-cache0 { cluster0_l2: l2-cache0 {
@@ -340,9 +340,9 @@
cache-level = <2>; cache-level = <2>;
}; };
cpu_pw20: cpu-pw20 { cpu_pw15: cpu-pw15 {
compatible = "arm,idle-state"; compatible = "arm,idle-state";
idle-state-name = "PW20"; idle-state-name = "PW15";
arm,psci-suspend-param = <0x0>; arm,psci-suspend-param = <0x0>;
entry-latency-us = <2000>; entry-latency-us = <2000>;
exit-latency-us = <2000>; exit-latency-us = <2000>;