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DT: rp1: add general-purpose clock source definitions

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GPCLKs have two parts - a clock divider and a clock input, routed out to
and in from a GPIO pad respectively. It follows that the clksrc_gpN
inputs can't be used unless the pad is also configured as a GPCLK, so
leave them disabled.

Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
This commit is contained in:
Jonathan Bell
2024-03-05 14:32:46 +00:00
committed by Dom Cobley
parent 8f9b2e3980
commit 0dc05f8eb1
1 changed files with 90 additions and 0 deletions
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90
arch/arm/boot/dts/broadcom/rp1.dtsi
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@@ -865,6 +865,36 @@
bias-disable;
};
rp1_gpclksrc0_gpio4: rp1_gpclksrc0_gpio4 {
function = "gpclk0";
pins = "gpio4";
bias-disable;
};
rp1_gpclksrc0_gpio20: rp1_gpclksrc0_gpio20 {
function = "gpclk0";
pins = "gpio20";
bias-disable;
};
rp1_gpclksrc1_gpio5: rp1_gpclksrc1_gpio5 {
function = "gpclk1";
pins = "gpio5";
bias-disable;
};
rp1_gpclksrc1_gpio18: rp1_gpclksrc1_gpio18 {
function = "gpclk1";
pins = "gpio18";
bias-disable;
};
rp1_gpclksrc1_gpio21: rp1_gpclksrc1_gpio21 {
function = "gpclk1";
pins = "gpio21";
bias-disable;
};
rp1_pwm1_gpio45: rp1_pwm1_gpio45 {
function = "pwm1";
pins = "gpio45";
@@ -1210,6 +1240,66 @@
clock-output-names = "clksrc_mipi1_dsi_byteclk";
clock-frequency = <72000000>;
};
/* GPIO derived clock sources. Each GPIO with a GPCLK function
* can drive its output from the respective GPCLK
* generator, and provide a clock source to other internal
* dividers. Add dummy sources here so that they can be overridden
* with overlays.
*/
clksrc_gp0: clksrc_gp0 {
status = "disabled";
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
clocks = <&rp1_clocks RP1_CLK_GP0>;
clock-output-names = "clksrc_gp0";
};
clksrc_gp1: clksrc_gp1 {
status = "disabled";
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
clocks = <&rp1_clocks RP1_CLK_GP1>;
clock-output-names = "clksrc_gp1";
};
clksrc_gp2: clksrc_gp2 {
status = "disabled";
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
#clock-cells = <0>;
clocks = <&rp1_clocks RP1_CLK_GP2>;
clock-output-names = "clksrc_gp2";
};
clksrc_gp3: clksrc_gp3 {
status = "disabled";
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
#clock-cells = <0>;
clocks = <&rp1_clocks RP1_CLK_GP3>;
clock-output-names = "clksrc_gp3";
};
clksrc_gp4: clksrc_gp4 {
status = "disabled";
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
clocks = <&rp1_clocks RP1_CLK_GP4>;
clock-output-names = "clksrc_gp4";
};
clksrc_gp5: clksrc_gp5 {
status = "disabled";
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
clocks = <&rp1_clocks RP1_CLK_GP5>;
clock-output-names = "clksrc_gp5";
};
};
/ {