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clk: bcm2835: Allow reparenting leaf clocks while they're running.

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This falls under the same "we can reprogram glitch-free as long as we
pause generation" rule as updating the div/frac fields.  This can be
used for runtime reclocking of V3D to manage power leakage.

Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Eric Anholt
2019-05-02 15:24:04 -07:00
committed by Dom Cobley
parent ced29cdae4
commit 0e7cc0af11
1 changed files with 16 additions and 3 deletions
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19
drivers/clk/bcm/clk-bcm2835.c
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@@ -1132,8 +1132,10 @@ static int bcm2835_clock_on(struct clk_hw *hw)
return 0; return 0;
} }
static int bcm2835_clock_set_rate(struct clk_hw *hw, static int bcm2835_clock_set_rate_and_parent(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate) unsigned long rate,
unsigned long parent_rate,
u8 parent)
{ {
struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
struct bcm2835_cprman *cprman = clock->cprman; struct bcm2835_cprman *cprman = clock->cprman;
@@ -1155,6 +1157,11 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw,
bcm2835_clock_wait_busy(clock); bcm2835_clock_wait_busy(clock);
} }
if (parent != 0xff) {
ctl &= ~(CM_SRC_MASK << CM_SRC_SHIFT);
ctl |= parent << CM_SRC_SHIFT;
}
ctl &= ~CM_FRAC; ctl &= ~CM_FRAC;
ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0; ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
cprman_write(cprman, data->ctl_reg, ctl); cprman_write(cprman, data->ctl_reg, ctl);
@@ -1166,6 +1173,12 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw,
return 0; return 0;
} }
static int bcm2835_clock_set_rate(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate)
{
return bcm2835_clock_set_rate_and_parent(hw, rate, parent_rate, 0xff);
}
static bool static bool
bcm2835_clk_is_pllc(struct clk_hw *hw) bcm2835_clk_is_pllc(struct clk_hw *hw)
{ {
@@ -1349,6 +1362,7 @@ static const struct clk_ops bcm2835_clock_clk_ops = {
.unprepare = bcm2835_clock_off, .unprepare = bcm2835_clock_off,
.recalc_rate = bcm2835_clock_get_rate, .recalc_rate = bcm2835_clock_get_rate,
.set_rate = bcm2835_clock_set_rate, .set_rate = bcm2835_clock_set_rate,
.set_rate_and_parent = bcm2835_clock_set_rate_and_parent,
.determine_rate = bcm2835_clock_determine_rate, .determine_rate = bcm2835_clock_determine_rate,
.set_parent = bcm2835_clock_set_parent, .set_parent = bcm2835_clock_set_parent,
.get_parent = bcm2835_clock_get_parent, .get_parent = bcm2835_clock_get_parent,
@@ -1531,7 +1545,6 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
init.ops = &bcm2835_vpu_clock_clk_ops; init.ops = &bcm2835_vpu_clock_clk_ops;
} else { } else {
init.ops = &bcm2835_clock_clk_ops; init.ops = &bcm2835_clock_clk_ops;
init.flags |= CLK_SET_PARENT_GATE;
/* If the clock wasn't actually enabled at boot, it's not /* If the clock wasn't actually enabled at boot, it's not
* critical. * critical.