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clk: bcm2835: Allow reparenting leaf clocks while they're running.
This falls under the same "we can reprogram glitch-free as long as we pause generation" rule as updating the div/frac fields. This can be used for runtime reclocking of V3D to manage power leakage. Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
@@ -1132,8 +1132,10 @@ static int bcm2835_clock_on(struct clk_hw *hw)
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return 0;
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}
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static int bcm2835_clock_set_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long parent_rate)
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static int bcm2835_clock_set_rate_and_parent(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate,
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u8 parent)
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{
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struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
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struct bcm2835_cprman *cprman = clock->cprman;
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@@ -1155,6 +1157,11 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw,
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bcm2835_clock_wait_busy(clock);
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}
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if (parent != 0xff) {
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ctl &= ~(CM_SRC_MASK << CM_SRC_SHIFT);
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ctl |= parent << CM_SRC_SHIFT;
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}
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ctl &= ~CM_FRAC;
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ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
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cprman_write(cprman, data->ctl_reg, ctl);
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@@ -1166,6 +1173,12 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw,
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return 0;
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}
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static int bcm2835_clock_set_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long parent_rate)
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{
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return bcm2835_clock_set_rate_and_parent(hw, rate, parent_rate, 0xff);
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}
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static bool
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bcm2835_clk_is_pllc(struct clk_hw *hw)
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{
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@@ -1349,6 +1362,7 @@ static const struct clk_ops bcm2835_clock_clk_ops = {
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.unprepare = bcm2835_clock_off,
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.recalc_rate = bcm2835_clock_get_rate,
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.set_rate = bcm2835_clock_set_rate,
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.set_rate_and_parent = bcm2835_clock_set_rate_and_parent,
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.determine_rate = bcm2835_clock_determine_rate,
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.set_parent = bcm2835_clock_set_parent,
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.get_parent = bcm2835_clock_get_parent,
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@@ -1531,7 +1545,6 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
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init.ops = &bcm2835_vpu_clock_clk_ops;
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} else {
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init.ops = &bcm2835_clock_clk_ops;
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init.flags |= CLK_SET_PARENT_GATE;
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/* If the clock wasn't actually enabled at boot, it's not
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* critical.
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