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arm64: dts: qcom: sc8280xp: Add USB-C-related DP blocks

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Add the two DisplayPort controllers that are attached to QMP phys for
providing display output on USB Type-C.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230213215619.1362566-2-quic_bjorande@quicinc.com
This commit is contained in:
Bjorn Andersson
2023-02-13 13:56:16 -08:00
committed by Bjorn Andersson
parent a8ecd17bb6
commit 19d3bb9075
1 changed files with 168 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

172
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
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@@ -3155,6 +3155,20 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
port@0 {
reg = <0>;
mdss0_intf0_out: endpoint {
remote-endpoint = <&mdss0_dp0_in>;
};
};
port@4 {
reg = <4>;
mdss0_intf4_out: endpoint {
remote-endpoint = <&mdss0_dp1_in>;
};
};
port@5 { port@5 {
reg = <5>; reg = <5>;
mdss0_intf5_out: endpoint { mdss0_intf5_out: endpoint {
@@ -3199,6 +3213,156 @@
}; };
}; };
mdss0_dp0: displayport-controller@ae90000 {
compatible = "qcom,sc8280xp-dp";
reg = <0 0xae90000 0 0x200>,
<0 0xae90200 0 0x200>,
<0 0xae90400 0 0x600>,
<0 0xae91000 0 0x400>,
<0 0xae91400 0 0x400>;
interrupt-parent = <&mdss0>;
interrupts = <12>;
clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
#sound-dai-cells = <0>;
operating-points-v2 = <&mdss0_dp0_opp_table>;
power-domains = <&rpmhpd SC8280XP_CX>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss0_dp0_in: endpoint {
remote-endpoint = <&mdss0_intf0_out>;
};
};
port@1 {
reg = <1>;
};
};
mdss0_dp0_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-270000000 {
opp-hz = /bits/ 64 <270000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-810000000 {
opp-hz = /bits/ 64 <810000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
mdss0_dp1: displayport-controller@ae98000 {
compatible = "qcom,sc8280xp-dp";
reg = <0 0xae98000 0 0x200>,
<0 0xae98200 0 0x200>,
<0 0xae98400 0 0x600>,
<0 0xae99000 0 0x400>,
<0 0xae99400 0 0x400>;
interrupt-parent = <&mdss0>;
interrupts = <13>;
clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
"ctrl_link_iface", "stream_pixel";
assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
<&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
#sound-dai-cells = <0>;
operating-points-v2 = <&mdss0_dp1_opp_table>;
power-domains = <&rpmhpd SC8280XP_CX>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss0_dp1_in: endpoint {
remote-endpoint = <&mdss0_intf4_out>;
};
};
port@1 {
reg = <1>;
};
};
mdss0_dp1_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-270000000 {
opp-hz = /bits/ 64 <270000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-810000000 {
opp-hz = /bits/ 64 <810000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
mdss0_dp2: displayport-controller@ae9a000 { mdss0_dp2: displayport-controller@ae9a000 {
compatible = "qcom,sc8280xp-dp"; compatible = "qcom,sc8280xp-dp";
reg = <0 0xae9a000 0 0x200>, reg = <0 0xae9a000 0 0x200>,
@@ -3387,10 +3551,10 @@
clocks = <&gcc GCC_DISP_AHB_CLK>, clocks = <&gcc GCC_DISP_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>, <&sleep_clk>,
<0>, <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<0>, <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<0>, <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<0>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 0>,
<&mdss0_dp2_phy 1>, <&mdss0_dp2_phy 1>,
<&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 0>,