raspi/linux
1
0
Fork 1
mirror of https://github.com/raspberrypi/linux.git synced 2025-12-06 01:49:46 +00:00
Code Issues Projects Releases Wiki Activity

clk: at91: sama7g5: fix parents of PDMCs' GCLK

Browse Source 
Audio PLL can be used as parent by the GCLKs of PDMCs.

Fixes: cb783bbbcf ("clk: at91: sama7g5: add clock support for sama7g5")
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220304182616.1920392-1-codrin.ciubotariu@microchip.com
This commit is contained in:
Codrin Ciubotariu
2022-03-04 20:26:16 +02:00
committed by Nicolas Ferre
parent a5ab04af49
commit 1a944729d8
1 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/clk/at91/sama7g5.c
View File

@@ -699,16 +699,16 @@ static const struct {
{ .n = "pdmc0_gclk", { .n = "pdmc0_gclk",
.id = 68, .id = 68,
.r = { .max = 50000000 }, .r = { .max = 50000000 },
.pp = { "syspll_divpmcck", "baudpll_divpmcck", }, .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
.pp_mux_table = { 5, 8, }, .pp_mux_table = { 5, 9, },
.pp_count = 2, .pp_count = 2,
.pp_chg_id = INT_MIN, }, .pp_chg_id = INT_MIN, },
{ .n = "pdmc1_gclk", { .n = "pdmc1_gclk",
.id = 69, .id = 69,
.r = { .max = 50000000, }, .r = { .max = 50000000, },
.pp = { "syspll_divpmcck", "baudpll_divpmcck", }, .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
.pp_mux_table = { 5, 8, }, .pp_mux_table = { 5, 9, },
.pp_count = 2, .pp_count = 2,
.pp_chg_id = INT_MIN, }, .pp_chg_id = INT_MIN, },