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drm/msm/dpu: fix len of sc7180 ctl blocks

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[ Upstream commit ce6bd00abc ]

Change sc7180's ctl block len to 0x1dc.

Fixes: 7bdc0c4b81 ("msm:disp:dpu1: add support for display for SC7180 target")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/522210/
Link: https://lore.kernel.org/r/20230211231259.1308718-5-dmitry.baryshkov@linaro.org
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Dmitry Baryshkov
2023-02-12 01:12:13 +02:00
committed by Greg Kroah-Hartman
parent f45cf3ae30
commit 1ef5491ca2
1 changed files with 3 additions and 3 deletions
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6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
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@@ -607,19 +607,19 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = {
static const struct dpu_ctl_cfg sc7180_ctl[] = { static const struct dpu_ctl_cfg sc7180_ctl[] = {
{ {
.name = "ctl_0", .id = CTL_0, .name = "ctl_0", .id = CTL_0,
.base = 0x1000, .len = 0xE4, .base = 0x1000, .len = 0x1dc,
.features = BIT(DPU_CTL_ACTIVE_CFG), .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, },
{ {
.name = "ctl_1", .id = CTL_1, .name = "ctl_1", .id = CTL_1,
.base = 0x1200, .len = 0xE4, .base = 0x1200, .len = 0x1dc,
.features = BIT(DPU_CTL_ACTIVE_CFG), .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, },
{ {
.name = "ctl_2", .id = CTL_2, .name = "ctl_2", .id = CTL_2,
.base = 0x1400, .len = 0xE4, .base = 0x1400, .len = 0x1dc,
.features = BIT(DPU_CTL_ACTIVE_CFG), .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, },