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arm64: dts: imx8mp-phyboard-pollux-rdk: add etml panel support
The imx8mp-phyboard-pollux has on-board lvds interface connections. An edt,etml1010g3dra panel is supported for this interface. Add device tree nodes for backlight and panel. Signed-off-by: Yannic Moog <y.moog@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
@@ -19,6 +19,30 @@
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stdout-path = &uart1;
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};
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backlight_lvds: backlight {
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compatible = "pwm-backlight";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lvds1>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <11>;
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enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
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num-interpolated-steps = <2>;
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power-supply = <®_lvds1_reg_en>;
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pwms = <&pwm3 0 50000 0>;
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};
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panel1_lvds: panel-lvds {
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compatible = "edt,etml1010g3dra";
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backlight = <&backlight_lvds>;
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power-supply = <®_vcc_3v3_sw>;
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port {
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panel1_in: endpoint {
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remote-endpoint = <&ldb_lvds_ch1>;
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};
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};
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};
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reg_can1_stby: regulator-can1-stby {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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@@ -39,6 +63,15 @@
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regulator-name = "can2-stby";
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};
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reg_lvds1_reg_en: regulator-lvds1 {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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regulator-max-microvolt = <1200000>;
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regulator-min-microvolt = <1200000>;
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regulator-name = "lvds1_reg_en";
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};
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reg_usb1_vbus: regulator-usb1-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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@@ -61,6 +94,13 @@
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startup-delay-us = <100>;
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off-on-delay-us = <12000>;
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};
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reg_vcc_3v3_sw: regulator-vcc-3v3-sw {
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compatible = "regulator-fixed";
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regulator-name = "VCC_3V3_SW";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&eqos {
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@@ -135,10 +175,32 @@
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};
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};
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&lcdif2 {
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status = "okay";
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};
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&lvds_bridge {
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status = "okay";
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ports {
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port@2 {
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ldb_lvds_ch1: endpoint {
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remote-endpoint = <&panel1_in>;
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};
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};
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};
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};
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&snvs_pwrkey {
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status = "okay";
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};
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&pwm3 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm3>;
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};
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/* debug console */
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&uart1 {
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pinctrl-names = "default";
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@@ -289,6 +351,18 @@
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>;
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};
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pinctrl_lvds1: lvds1grp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12
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>;
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};
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pinctrl_pwm3: pwm3grp {
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fsl,pins = <
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MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x12
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
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