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amdgpu/gmc_v9: save/restore sdpif regs during S3

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commit a3ed353cf8 upstream.

fixes S3 issue with IOMMU + S/G  enabled @ 64M VRAM.

Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Shirish S
2020-01-27 16:35:24 +05:30
committed by Greg Kroah-Hartman
parent 8e7ddaf759
commit 386a71f635
3 changed files with 39 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
View File

@@ -157,6 +157,7 @@ struct amdgpu_gmc {
uint32_t srbm_soft_reset; uint32_t srbm_soft_reset;
bool prt_warning; bool prt_warning;
uint64_t stolen_size; uint64_t stolen_size;
uint32_t sdpif_register;
/* apertures */ /* apertures */
u64 shared_aperture_start; u64 shared_aperture_start;
u64 shared_aperture_end; u64 shared_aperture_end;

37
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
View File

@@ -1382,6 +1382,19 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
} }
} }
/**
* gmc_v9_0_restore_registers - restores regs
*
* @adev: amdgpu_device pointer
*
* This restores register values, saved at suspend.
*/
static void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
{
if (adev->asic_type == CHIP_RAVEN)
WREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
}
/** /**
* gmc_v9_0_gart_enable - gart enable * gmc_v9_0_gart_enable - gart enable
* *
@@ -1478,6 +1491,20 @@ static int gmc_v9_0_hw_init(void *handle)
return r; return r;
} }
/**
* gmc_v9_0_save_registers - saves regs
*
* @adev: amdgpu_device pointer
*
* This saves potential register values that should be
* restored upon resume
*/
static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
{
if (adev->asic_type == CHIP_RAVEN)
adev->gmc.sdpif_register = RREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
}
/** /**
* gmc_v9_0_gart_disable - gart disable * gmc_v9_0_gart_disable - gart disable
* *
@@ -1514,9 +1541,16 @@ static int gmc_v9_0_hw_fini(void *handle)
static int gmc_v9_0_suspend(void *handle) static int gmc_v9_0_suspend(void *handle)
{ {
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
return gmc_v9_0_hw_fini(adev); r = gmc_v9_0_hw_fini(adev);
if (r)
return r;
gmc_v9_0_save_registers(adev);
return 0;
} }
static int gmc_v9_0_resume(void *handle) static int gmc_v9_0_resume(void *handle)
@@ -1524,6 +1558,7 @@ static int gmc_v9_0_resume(void *handle)
int r; int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
gmc_v9_0_restore_registers(adev);
r = gmc_v9_0_hw_init(adev); r = gmc_v9_0_hw_init(adev);
if (r) if (r)
return r; return r;

2
drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h
View File

@@ -7376,6 +7376,8 @@
#define mmCRTC4_CRTC_DRR_CONTROL 0x0f3e #define mmCRTC4_CRTC_DRR_CONTROL 0x0f3e
#define mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX 2 #define mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x395d
#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2
// addressBlock: dce_dc_fmt4_dispdec // addressBlock: dce_dc_fmt4_dispdec
// base address: 0x2000 // base address: 0x2000