raspi/linux
1
0
Fork 1
mirror of https://github.com/raspberrypi/linux.git synced 2025-12-25 19:42:19 +00:00
Code Issues Projects Releases Wiki Activity

riscv: convert to generic syscall table

Browse Source 
The uapi/asm/unistd_{32,64}.h and asm/syscall_table_{32,64}.h headers can
now be generated from scripts/syscall.tbl, which makes this consistent
with the other architectures that have their own syscall.tbl.

riscv has two extra system call that gets added to scripts/syscall.tbl.

The newstat and rlimit entries in the syscall_abis_64 line are for system
calls that were part of the generic ABI when riscv64 got added but are
no longer enabled by default for new architectures. Both riscv32 and
riscv64 also implement memfd_secret, which is optional for all
architectures.

Unlike all the other 32-bit architectures, the time32 and stat64
sets of syscalls are not enabled on riscv32.

Both the user visible side of asm/unistd.h and the internal syscall
table in the kernel should have the same effective contents after this.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2024-04-24 09:14:39 +02:00
parent 77122bf9e3
commit 3db80c999d
9 changed files with 40 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/riscv/include/uapi/asm/Kbuild
View File

@@ -1 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
syscall-y += unistd_32.h
syscall-y += unistd_64.h

40
arch/riscv/include/uapi/asm/unistd.h
View File

@@ -14,40 +14,10 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#include <asm/bitsperlong.h>
#if defined(__LP64__) && !defined(__SYSCALL_COMPAT)
#define __ARCH_WANT_NEW_STAT
#define __ARCH_WANT_SET_GET_RLIMIT
#endif /* __LP64__ */
#define __ARCH_WANT_MEMFD_SECRET
#include <asm-generic/unistd.h>
/*
* Allows the instruction cache to be flushed from userspace. Despite RISC-V
* having a direct 'fence.i' instruction available to userspace (which we
* can't trap!), that's not actually viable when running on Linux because the
* kernel might schedule a process on another hart. There is no way for
* userspace to handle this without invoking the kernel (as it doesn't know the
* thread->hart mappings), so we've defined a RISC-V specific system call to
* flush the instruction cache.
*
* __NR_riscv_flush_icache is defined to flush the instruction cache over an
* address range, with the flush applying to either all threads or just the
* caller. We don't currently do anything with the address range, that's just
* in there for forwards compatibility.
*/
#ifndef __NR_riscv_flush_icache
#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
#if __BITS_PER_LONG == 64
#include <asm/unistd_64.h>
#else
#include <asm/unistd_32.h>
#endif
__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)
/*
* Allows userspace to query the kernel for CPU architecture and
* microarchitecture details across a given set of CPUs.
*/
#ifndef __NR_riscv_hwprobe
#define __NR_riscv_hwprobe (__NR_arch_specific_syscall + 14)
#endif
__SYSCALL(__NR_riscv_hwprobe, sys_riscv_hwprobe)