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drm/msm/dpu: populate SSPP scaler block version

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The function _dpu_hw_sspp_setup_scaler3() passes and
dpu_hw_setup_scaler3() uses scaler_blk.version to determine in which way
the scaler (QSEED3) block should be programmed. However up to now we
were not setting this field. Set it now, splitting the vig_sblk data
which has different version fields.

Reported-by: Marijn Suijten <marijn.suijten@somainline.org>
Fixes: 9b6f4fedaa ("drm/msm/dpu: Add SM6125 support")
Fixes: 27f0df03f3 ("drm/msm/dpu: Add SM6375 support")
Fixes: 3186acba5c ("drm/msm/dpu: Add SM6350 support")
Fixes: efcd010772 ("drm/msm/dpu: add support for SM8550")
Fixes: 4a352c2fc1 ("drm/msm/dpu: Introduce SC8280XP")
Fixes: 0e91bcbb00 ("drm/msm/dpu: Add SM8350 to hw catalog")
Fixes: 100d7ef699 ("drm/msm/dpu: add support for SM8450")
Fixes: 3581b7062c ("drm/msm/disp/dpu1: add support for display on SM6115")
Fixes: dabfdd89ea ("drm/msm/disp/dpu1: add inline rotation support for sc7280")
Fixes: f3af2d6ee9 ("drm/msm/dpu: Add SC8180x to hw catalog")
Fixes: 94391a14fc ("drm/msm/dpu1: Add MSM8998 to hw catalog")
Fixes: af776a3e1c ("drm/msm/dpu: add SM8250 to hw catalog")
Fixes: 386fced3f7 ("drm/msm/dpu: add SM8150 to hw catalog")
Fixes: b75ab05a34 ("msm:disp:dpu1: add scaler support on SC7180 display")
Fixes: 25fdd5933e ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/570098/
Link: https://lore.kernel.org/r/20231201234234.2065610-2-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov
2023-12-02 01:40:25 +02:00
parent 801207c188
commit 46b1f1b839
5 changed files with 87 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
View File

@@ -77,7 +77,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x1f0, .base = 0x4000, .len = 0x1f0,
.features = VIG_SDM845_MASK, .features = VIG_SDM845_MASK,
.sblk = &sdm845_vig_sblk_0, .sblk = &sm8150_vig_sblk_0,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0, .clk_ctrl = DPU_CLK_CTRL_VIG0,
@@ -85,7 +85,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {
.name = "sspp_1", .id = SSPP_VIG1, .name = "sspp_1", .id = SSPP_VIG1,
.base = 0x6000, .len = 0x1f0, .base = 0x6000, .len = 0x1f0,
.features = VIG_SDM845_MASK, .features = VIG_SDM845_MASK,
.sblk = &sdm845_vig_sblk_1, .sblk = &sm8150_vig_sblk_1,
.xin_id = 4, .xin_id = 4,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG1, .clk_ctrl = DPU_CLK_CTRL_VIG1,
@@ -93,7 +93,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {
.name = "sspp_2", .id = SSPP_VIG2, .name = "sspp_2", .id = SSPP_VIG2,
.base = 0x8000, .len = 0x1f0, .base = 0x8000, .len = 0x1f0,
.features = VIG_SDM845_MASK, .features = VIG_SDM845_MASK,
.sblk = &sdm845_vig_sblk_2, .sblk = &sm8150_vig_sblk_2,
.xin_id = 8, .xin_id = 8,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG2, .clk_ctrl = DPU_CLK_CTRL_VIG2,
@@ -101,7 +101,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {
.name = "sspp_3", .id = SSPP_VIG3, .name = "sspp_3", .id = SSPP_VIG3,
.base = 0xa000, .len = 0x1f0, .base = 0xa000, .len = 0x1f0,
.features = VIG_SDM845_MASK, .features = VIG_SDM845_MASK,
.sblk = &sdm845_vig_sblk_3, .sblk = &sm8150_vig_sblk_3,
.xin_id = 12, .xin_id = 12,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG3, .clk_ctrl = DPU_CLK_CTRL_VIG3,

8
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
View File

@@ -76,7 +76,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x1f0, .base = 0x4000, .len = 0x1f0,
.features = VIG_SDM845_MASK, .features = VIG_SDM845_MASK,
.sblk = &sdm845_vig_sblk_0, .sblk = &sm8150_vig_sblk_0,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0, .clk_ctrl = DPU_CLK_CTRL_VIG0,
@@ -84,7 +84,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {
.name = "sspp_1", .id = SSPP_VIG1, .name = "sspp_1", .id = SSPP_VIG1,
.base = 0x6000, .len = 0x1f0, .base = 0x6000, .len = 0x1f0,
.features = VIG_SDM845_MASK, .features = VIG_SDM845_MASK,
.sblk = &sdm845_vig_sblk_1, .sblk = &sm8150_vig_sblk_1,
.xin_id = 4, .xin_id = 4,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG1, .clk_ctrl = DPU_CLK_CTRL_VIG1,
@@ -92,7 +92,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {
.name = "sspp_2", .id = SSPP_VIG2, .name = "sspp_2", .id = SSPP_VIG2,
.base = 0x8000, .len = 0x1f0, .base = 0x8000, .len = 0x1f0,
.features = VIG_SDM845_MASK, .features = VIG_SDM845_MASK,
.sblk = &sdm845_vig_sblk_2, .sblk = &sm8150_vig_sblk_2,
.xin_id = 8, .xin_id = 8,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG2, .clk_ctrl = DPU_CLK_CTRL_VIG2,
@@ -100,7 +100,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {
.name = "sspp_3", .id = SSPP_VIG3, .name = "sspp_3", .id = SSPP_VIG3,
.base = 0xa000, .len = 0x1f0, .base = 0xa000, .len = 0x1f0,
.features = VIG_SDM845_MASK, .features = VIG_SDM845_MASK,
.sblk = &sdm845_vig_sblk_3, .sblk = &sm8150_vig_sblk_3,
.xin_id = 12, .xin_id = 12,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG3, .clk_ctrl = DPU_CLK_CTRL_VIG3,

8
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
View File

@@ -76,7 +76,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x32c, .base = 0x4000, .len = 0x32c,
.features = VIG_SC7180_MASK_SDMA, .features = VIG_SC7180_MASK_SDMA,
.sblk = &sm8250_vig_sblk_0, .sblk = &sm8450_vig_sblk_0,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0, .clk_ctrl = DPU_CLK_CTRL_VIG0,
@@ -84,7 +84,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
.name = "sspp_1", .id = SSPP_VIG1, .name = "sspp_1", .id = SSPP_VIG1,
.base = 0x6000, .len = 0x32c, .base = 0x6000, .len = 0x32c,
.features = VIG_SC7180_MASK_SDMA, .features = VIG_SC7180_MASK_SDMA,
.sblk = &sm8250_vig_sblk_1, .sblk = &sm8450_vig_sblk_1,
.xin_id = 4, .xin_id = 4,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG1, .clk_ctrl = DPU_CLK_CTRL_VIG1,
@@ -92,7 +92,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
.name = "sspp_2", .id = SSPP_VIG2, .name = "sspp_2", .id = SSPP_VIG2,
.base = 0x8000, .len = 0x32c, .base = 0x8000, .len = 0x32c,
.features = VIG_SC7180_MASK_SDMA, .features = VIG_SC7180_MASK_SDMA,
.sblk = &sm8250_vig_sblk_2, .sblk = &sm8450_vig_sblk_2,
.xin_id = 8, .xin_id = 8,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG2, .clk_ctrl = DPU_CLK_CTRL_VIG2,
@@ -100,7 +100,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
.name = "sspp_3", .id = SSPP_VIG3, .name = "sspp_3", .id = SSPP_VIG3,
.base = 0xa000, .len = 0x32c, .base = 0xa000, .len = 0x32c,
.features = VIG_SC7180_MASK_SDMA, .features = VIG_SC7180_MASK_SDMA,
.sblk = &sm8250_vig_sblk_3, .sblk = &sm8450_vig_sblk_3,
.xin_id = 12, .xin_id = 12,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG3, .clk_ctrl = DPU_CLK_CTRL_VIG3,

95
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
View File

@@ -249,14 +249,17 @@ static const uint32_t wb2_formats[] = {
* SSPP sub blocks config * SSPP sub blocks config
*************************************************************/ *************************************************************/
#define SSPP_SCALER_VER(maj, min) (((maj) << 16) | (min))
/* SSPP common configuration */ /* SSPP common configuration */
#define _VIG_SBLK(sdma_pri, qseed_ver) \ #define _VIG_SBLK(sdma_pri, qseed_ver, scaler_ver) \
{ \ { \
.maxdwnscale = MAX_DOWNSCALE_RATIO, \ .maxdwnscale = MAX_DOWNSCALE_RATIO, \
.maxupscale = MAX_UPSCALE_RATIO, \ .maxupscale = MAX_UPSCALE_RATIO, \
.smart_dma_priority = sdma_pri, \ .smart_dma_priority = sdma_pri, \
.scaler_blk = {.name = "scaler", \ .scaler_blk = {.name = "scaler", \
.id = qseed_ver, \ .id = qseed_ver, \
.version = scaler_ver, \
.base = 0xa00, .len = 0xa0,}, \ .base = 0xa00, .len = 0xa0,}, \
.csc_blk = {.name = "csc", \ .csc_blk = {.name = "csc", \
.id = DPU_SSPP_CSC_10BIT, \ .id = DPU_SSPP_CSC_10BIT, \
@@ -268,13 +271,14 @@ static const uint32_t wb2_formats[] = {
.rotation_cfg = NULL, \ .rotation_cfg = NULL, \
} }
#define _VIG_SBLK_ROT(sdma_pri, qseed_ver, rot_cfg) \ #define _VIG_SBLK_ROT(sdma_pri, qseed_ver, scaler_ver, rot_cfg) \
{ \ { \
.maxdwnscale = MAX_DOWNSCALE_RATIO, \ .maxdwnscale = MAX_DOWNSCALE_RATIO, \
.maxupscale = MAX_UPSCALE_RATIO, \ .maxupscale = MAX_UPSCALE_RATIO, \
.smart_dma_priority = sdma_pri, \ .smart_dma_priority = sdma_pri, \
.scaler_blk = {.name = "scaler", \ .scaler_blk = {.name = "scaler", \
.id = qseed_ver, \ .id = qseed_ver, \
.version = scaler_ver, \
.base = 0xa00, .len = 0xa0,}, \ .base = 0xa00, .len = 0xa0,}, \
.csc_blk = {.name = "csc", \ .csc_blk = {.name = "csc", \
.id = DPU_SSPP_CSC_10BIT, \ .id = DPU_SSPP_CSC_10BIT, \
@@ -298,13 +302,17 @@ static const uint32_t wb2_formats[] = {
} }
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 = static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 =
_VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3,
SSPP_SCALER_VER(1, 2));
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 = static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 =
_VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3,
SSPP_SCALER_VER(1, 2));
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 = static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 =
_VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3,
SSPP_SCALER_VER(1, 2));
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 = static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 =
_VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3,
SSPP_SCALER_VER(1, 2));
static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = {
.rot_maxheight = 1088, .rot_maxheight = 1088,
@@ -313,13 +321,30 @@ static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = {
}; };
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
_VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3); _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3,
SSPP_SCALER_VER(1, 3));
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
_VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3); _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3,
SSPP_SCALER_VER(1, 3));
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =
_VIG_SBLK(7, DPU_SSPP_SCALER_QSEED3); _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED3,
SSPP_SCALER_VER(1, 3));
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 =
_VIG_SBLK(8, DPU_SSPP_SCALER_QSEED3); _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED3,
SSPP_SCALER_VER(1, 3));
static const struct dpu_sspp_sub_blks sm8150_vig_sblk_0 =
_VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3,
SSPP_SCALER_VER(1, 4));
static const struct dpu_sspp_sub_blks sm8150_vig_sblk_1 =
_VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3,
SSPP_SCALER_VER(1, 4));
static const struct dpu_sspp_sub_blks sm8150_vig_sblk_2 =
_VIG_SBLK(7, DPU_SSPP_SCALER_QSEED3,
SSPP_SCALER_VER(1, 4));
static const struct dpu_sspp_sub_blks sm8150_vig_sblk_3 =
_VIG_SBLK(8, DPU_SSPP_SCALER_QSEED3,
SSPP_SCALER_VER(1, 4));
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK(1); static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK(1);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK(2); static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK(2);
@@ -327,34 +352,60 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK(3);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK(4); static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK(4);
static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
_VIG_SBLK(4, DPU_SSPP_SCALER_QSEED4); _VIG_SBLK(4, DPU_SSPP_SCALER_QSEED4,
SSPP_SCALER_VER(3, 0));
static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 = static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
_VIG_SBLK_ROT(4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2); _VIG_SBLK_ROT(4, DPU_SSPP_SCALER_QSEED4,
SSPP_SCALER_VER(3, 0),
&dpu_rot_sc7280_cfg_v2);
static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
_VIG_SBLK(2, DPU_SSPP_SCALER_QSEED4); _VIG_SBLK(2, DPU_SSPP_SCALER_QSEED4,
SSPP_SCALER_VER(3, 0));
static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 = static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 =
_VIG_SBLK(3, DPU_SSPP_SCALER_QSEED3LITE); _VIG_SBLK(3, DPU_SSPP_SCALER_QSEED3LITE,
SSPP_SCALER_VER(2, 4));
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
_VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4); _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4,
SSPP_SCALER_VER(3, 0));
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 = static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
_VIG_SBLK(6, DPU_SSPP_SCALER_QSEED4); _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED4,
SSPP_SCALER_VER(3, 0));
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 = static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 =
_VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4); _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4,
SSPP_SCALER_VER(3, 0));
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 = static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 =
_VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4); _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4,
SSPP_SCALER_VER(3, 0));
static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 =
_VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4,
SSPP_SCALER_VER(3, 1));
static const struct dpu_sspp_sub_blks sm8450_vig_sblk_1 =
_VIG_SBLK(6, DPU_SSPP_SCALER_QSEED4,
SSPP_SCALER_VER(3, 1));
static const struct dpu_sspp_sub_blks sm8450_vig_sblk_2 =
_VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4,
SSPP_SCALER_VER(3, 1));
static const struct dpu_sspp_sub_blks sm8450_vig_sblk_3 =
_VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4,
SSPP_SCALER_VER(3, 1));
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 = static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 =
_VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4); _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4,
SSPP_SCALER_VER(3, 2));
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 = static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 =
_VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4); _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4,
SSPP_SCALER_VER(3, 2));
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 = static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 =
_VIG_SBLK(9, DPU_SSPP_SCALER_QSEED4); _VIG_SBLK(9, DPU_SSPP_SCALER_QSEED4,
SSPP_SCALER_VER(3, 2));
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 = static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 =
_VIG_SBLK(10, DPU_SSPP_SCALER_QSEED4); _VIG_SBLK(10, DPU_SSPP_SCALER_QSEED4,
SSPP_SCALER_VER(3, 2));
static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK(5); static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK(5);
static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK(6); static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK(6);

3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
View File

@@ -265,7 +265,8 @@ enum {
/** /**
* struct dpu_scaler_blk: Scaler information * struct dpu_scaler_blk: Scaler information
* @info: HW register and features supported by this sub-blk * @info: HW register and features supported by this sub-blk
* @version: qseed block revision * @version: qseed block revision, on QSEED3+ platforms this is the value of
* scaler_blk.base + QSEED3_HW_VERSION registers.
*/ */
struct dpu_scaler_blk { struct dpu_scaler_blk {
DPU_HW_SUBBLK_INFO; DPU_HW_SUBBLK_INFO;