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drm/i915: Avoid TP3 on CHV

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commit ed63baaf84 upstream.

This patch removes TP3 support on CHV since there is no support
for HBR2 on this platform.

v2: rename the function to indicate it checks source rates (Jani)
v3: update comment to indicate TP3 dependency on HBR2 supported
    hardware (Jani)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
[Jani: fixed a couple of checkpatch warnings.]
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Thulasimani,Sivakumar
2015-08-18 15:30:37 +05:30
committed by Greg Kroah-Hartman
parent d0cd6730fd
commit 5598cbeda8
1 changed files with 22 additions and 8 deletions
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30
drivers/gpu/drm/i915/intel_dp.c
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@@ -1150,6 +1150,19 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
} }
static bool intel_dp_source_supports_hbr2(struct drm_device *dev)
{
/* WaDisableHBR2:skl */
if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
return false;
if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
(INTEL_INFO(dev)->gen >= 9))
return true;
else
return false;
}
static int static int
intel_dp_source_rates(struct drm_device *dev, const int **source_rates) intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
{ {
@@ -1163,12 +1176,8 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
*source_rates = default_rates; *source_rates = default_rates;
/* WaDisableHBR2:skl */ /* This depends on the fact that 5.4 is last value in the array */
if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) if (intel_dp_source_supports_hbr2(dev))
return (DP_LINK_BW_2_7 >> 3) + 1;
if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
(INTEL_INFO(dev)->gen >= 9))
return (DP_LINK_BW_5_4 >> 3) + 1; return (DP_LINK_BW_5_4 >> 3) + 1;
else else
return (DP_LINK_BW_2_7 >> 3) + 1; return (DP_LINK_BW_2_7 >> 3) + 1;
@@ -3784,10 +3793,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
} }
} }
/* Training Pattern 3 support, both source and sink */ /* Training Pattern 3 support, Intel platforms that support HBR2 alone
* have support for TP3 hence that check is used along with dpcd check
* to ensure TP3 can be enabled.
* SKL < B0: due it's WaDisableHBR2 is the only exception where TP3 is
* supported but still not enabled.
*/
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED && intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
(IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) { intel_dp_source_supports_hbr2(dev)) {
intel_dp->use_tps3 = true; intel_dp->use_tps3 = true;
DRM_DEBUG_KMS("Displayport TPS3 supported\n"); DRM_DEBUG_KMS("Displayport TPS3 supported\n");
} else } else