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usb: xhci: add VLI_TRB_CACHE_BUG quirk

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The VL805 fetches up to 4 transfer TRBs at a time. TRB reads don't cross
a 64B boundary, and if a TRB is fetched and is not on a 64B boundary,
the read is sized up to the next 64B boundary.

However the VL805 implements a readahead prefetch for TRBs on a transfer
ring. This fetches the next 64B after any TRB read has happened. Near
the end of a ring segment, the prefetcher can read the first 64B of the
next page in physical memory and this is where the behaviour causes a
bug.

The controller does not tag reads with which endpoint they are for, so
if the start of the next page is a ring segment used by a victim
endpoint, and the victim endpoint is about to fetch TRBs from the start
of the segment, the victim endpoint will read from the prefetched data
and not perform a read to main memory. If the data is stale, the ring
cycle state bit may not be correct and the endpoint will silently halt.

Adjust trbs_per_seg for transfer rings allocated for this controller.

See https://github.com/raspberrypi/linux/issues/4685

Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
This commit is contained in:
Jonathan Bell
2021-12-13 16:04:03 +00:00
committed by Dom Cobley
parent 64b014bb10
commit 5a57342810
3 changed files with 13 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/usb/host/xhci-mem.c
View File

@@ -393,6 +393,17 @@ struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
return ring; return ring;
ring->trbs_per_seg = TRBS_PER_SEGMENT; ring->trbs_per_seg = TRBS_PER_SEGMENT;
/*
* The Via VL805 has a bug where cache readahead will fetch off the end
* of a page if the Link TRB of a transfer ring is in the last 4 slots.
* Where there are consecutive physical pages containing ring segments,
* this can cause a desync between the controller's view of a ring
* and the host.
*/
if (xhci->quirks & XHCI_VLI_TRB_CACHE_BUG &&
type != TYPE_EVENT && type != TYPE_COMMAND)
ring->trbs_per_seg -= 4;
ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg, ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
&ring->last_seg, num_segs, ring->trbs_per_seg, &ring->last_seg, num_segs, ring->trbs_per_seg,
cycle_state, type, max_packet, flags); cycle_state, type, max_packet, flags);

1
drivers/usb/host/xhci-pci.c
View File

@@ -490,6 +490,7 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
xhci->quirks |= XHCI_LPM_SUPPORT; xhci->quirks |= XHCI_LPM_SUPPORT;
xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS; xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
xhci->quirks |= XHCI_AVOID_DQ_ON_LINK; xhci->quirks |= XHCI_AVOID_DQ_ON_LINK;
xhci->quirks |= XHCI_VLI_TRB_CACHE_BUG;
} }
if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&

1
drivers/usb/host/xhci.h
View File

@@ -1907,6 +1907,7 @@ struct xhci_hcd {
#define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
#define XHCI_RESET_TO_DEFAULT BIT_ULL(44) #define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
#define XHCI_AVOID_DQ_ON_LINK BIT_ULL(45) #define XHCI_AVOID_DQ_ON_LINK BIT_ULL(45)
#define XHCI_VLI_TRB_CACHE_BUG BIT_ULL(46)
unsigned int num_active_eps; unsigned int num_active_eps;
unsigned int limit_active_eps; unsigned int limit_active_eps;