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usb: xhci: add VLI_TRB_CACHE_BUG quirk
The VL805 fetches up to 4 transfer TRBs at a time. TRB reads don't cross a 64B boundary, and if a TRB is fetched and is not on a 64B boundary, the read is sized up to the next 64B boundary. However the VL805 implements a readahead prefetch for TRBs on a transfer ring. This fetches the next 64B after any TRB read has happened. Near the end of a ring segment, the prefetcher can read the first 64B of the next page in physical memory and this is where the behaviour causes a bug. The controller does not tag reads with which endpoint they are for, so if the start of the next page is a ring segment used by a victim endpoint, and the victim endpoint is about to fetch TRBs from the start of the segment, the victim endpoint will read from the prefetched data and not perform a read to main memory. If the data is stale, the ring cycle state bit may not be correct and the endpoint will silently halt. Adjust trbs_per_seg for transfer rings allocated for this controller. See https://github.com/raspberrypi/linux/issues/4685 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
This commit is contained in:
committed by
Dom Cobley
parent
64b014bb10
commit
5a57342810
@@ -393,6 +393,17 @@ struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
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return ring;
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ring->trbs_per_seg = TRBS_PER_SEGMENT;
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/*
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* The Via VL805 has a bug where cache readahead will fetch off the end
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* of a page if the Link TRB of a transfer ring is in the last 4 slots.
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* Where there are consecutive physical pages containing ring segments,
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* this can cause a desync between the controller's view of a ring
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* and the host.
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*/
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if (xhci->quirks & XHCI_VLI_TRB_CACHE_BUG &&
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type != TYPE_EVENT && type != TYPE_COMMAND)
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ring->trbs_per_seg -= 4;
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ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
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&ring->last_seg, num_segs, ring->trbs_per_seg,
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cycle_state, type, max_packet, flags);
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@@ -490,6 +490,7 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
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xhci->quirks |= XHCI_LPM_SUPPORT;
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xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
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xhci->quirks |= XHCI_AVOID_DQ_ON_LINK;
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xhci->quirks |= XHCI_VLI_TRB_CACHE_BUG;
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}
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if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
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@@ -1907,6 +1907,7 @@ struct xhci_hcd {
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#define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
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#define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
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#define XHCI_AVOID_DQ_ON_LINK BIT_ULL(45)
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#define XHCI_VLI_TRB_CACHE_BUG BIT_ULL(46)
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unsigned int num_active_eps;
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unsigned int limit_active_eps;
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