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arm64: dts: sdm845: Add qspi opps and power-domains

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Add the power domain supporting performance state and the corresponding
OPP tables for the qspi device on sdm845

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1593769293-6354-3-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Rajendra Nayak
2020-07-03 15:11:32 +05:30
committed by Bjorn Andersson
parent 54b50f2153
commit 5b4de2f8b5
1 changed files with 26 additions and 0 deletions
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26
arch/arm64/boot/dts/qcom/sdm845.dtsi
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@@ -3200,6 +3200,30 @@
status = "disabled"; status = "disabled";
}; };
qspi_opp_table: qspi-opp-table {
compatible = "operating-points-v2";
opp-19200000 {
opp-hz = /bits/ 64 <19200000>;
required-opps = <&rpmhpd_opp_min_svs>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-150000000 {
opp-hz = /bits/ 64 <150000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
qspi: spi@88df000 { qspi: spi@88df000 {
compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
reg = <0 0x088df000 0 0x600>; reg = <0 0x088df000 0 0x600>;
@@ -3209,6 +3233,8 @@
clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<&gcc GCC_QSPI_CORE_CLK>; <&gcc GCC_QSPI_CORE_CLK>;
clock-names = "iface", "core"; clock-names = "iface", "core";
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qspi_opp_table>;
status = "disabled"; status = "disabled";
}; };