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phy: rockchip: phy-rockchip-inno-csidphy: allow writes to grf register 0

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[ Upstream commit 8c7c19466c ]

The driver for the Rockchip MIPI CSI-2 DPHY uses GRF register offset
value 0 to sort out undefined registers. However, the RK3588 CSIDPHY GRF
this offset is perfectly fine (in fact, register 0 is the only one in
this register file).
Introduce a boolean variable to indicate valid registers and allow writes
to register 0.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Michael Riesch <michael.riesch@collabora.com>
Link: https://lore.kernel.org/r/20250616-rk3588-csi-dphy-v4-4-a4f340a7f0cf@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Michael Riesch
2025-09-03 19:04:52 +02:00
committed by Greg Kroah-Hartman
parent 1539159cf2
commit 66bb2a020d
1 changed files with 3 additions and 2 deletions
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5
drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
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@@ -87,10 +87,11 @@ struct dphy_reg {
u32 offset; u32 offset;
u32 mask; u32 mask;
u32 shift; u32 shift;
u8 valid;
}; };
#define PHY_REG(_offset, _width, _shift) \ #define PHY_REG(_offset, _width, _shift) \
{ .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, } { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, .valid = 1, }
static const struct dphy_reg rk1808_grf_dphy_regs[] = { static const struct dphy_reg rk1808_grf_dphy_regs[] = {
[GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 0), [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 0),
@@ -145,7 +146,7 @@ static inline void write_grf_reg(struct rockchip_inno_csidphy *priv,
const struct dphy_drv_data *drv_data = priv->drv_data; const struct dphy_drv_data *drv_data = priv->drv_data;
const struct dphy_reg *reg = &drv_data->grf_regs[index]; const struct dphy_reg *reg = &drv_data->grf_regs[index];
if (reg->offset) if (reg->valid)
regmap_write(priv->grf, reg->offset, regmap_write(priv->grf, reg->offset,
HIWORD_UPDATE(value, reg->mask, reg->shift)); HIWORD_UPDATE(value, reg->mask, reg->shift));
} }