From 78a686d41f1a42a80f82a717f672c49933d334df Mon Sep 17 00:00:00 2001 From: Nick Hollinghurst Date: Tue, 11 Jun 2024 10:20:38 +0100 Subject: [PATCH] drm: rp1: rp1-dsi: Don't enable clock until all lanes in stopstate Ensure receiver has a chance to see all lanes static in LP11 state before the clock lane transitions to HS mode, rather than starting it immediately. Signed-off-by: Nick Hollinghurst --- drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c b/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c index 9b13c5512d3d..fae5d13c74af 100644 --- a/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c +++ b/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c @@ -1434,7 +1434,7 @@ void rp1dsi_dsi_setup(struct rp1_dsi *dsi, struct drm_display_mode const *mode) if (timeout == 0) drm_err(dsi->drm, "RP1DSI: Time out waiting for PLL\n"); - DSI_WRITE(DSI_LPCLK_CTRL, 0x1); /* configure the requesthsclk */ + DSI_WRITE(DSI_LPCLK_CTRL, 0x0); /* clock off (start in LP11) */ DSI_WRITE(DSI_PHY_TST_CTRL0, 0x2); DSI_WRITE(DSI_PCKHDL_CFG, 1 << 2); /* allow bus turnaround */ DSI_WRITE(DSI_PWR_UP, 0x1); /* power up */ @@ -1458,6 +1458,10 @@ void rp1dsi_dsi_setup(struct rp1_dsi *dsi, struct drm_display_mode const *mode) if (timeout == 0) drm_err(dsi->drm, "RP1DSI: Time out waiting for lanes (%x %x)\n", mask, DSI_READ(DSI_PHY_STATUS)); + + usleep_range(5, 10); + DSI_WRITE(DSI_LPCLK_CTRL, 0x1); /* continuous clock */ + usleep_range(5, 10); } void rp1dsi_dsi_send(struct rp1_dsi *dsi, u32 hdr, int len, const u8 *buf)