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riscv: Update MIPS vendor id to 0x127

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[1] defines MIPS vendor id as 0x127. All previous MIPS RISC-V patches
were tested on QEMU, also modified to use 0x722 as MIPS_VENDOR_ID. This
new value should reflect real hardware.

[1] https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf

Fixes: a8fed1bc03 ("riscv: Add xmipsexectl as a vendor extension")
Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
Link: https://patch.msgid.link/20251113-mips-vendorid-v2-1-3279489b7f84@htecgroup.com
Cc: <stable@vger.kernel.org>
Signed-off-by: Paul WAlmsley <pjw@kernel.org>
This commit is contained in:
Chao-ying Fu
2025-11-13 17:10:32 +01:00
committed by Paul Walmsley
parent 4427259cc7
commit 91f815b707
1 changed files with 1 additions and 1 deletions
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2
arch/riscv/include/asm/vendorid_list.h
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@@ -7,8 +7,8 @@
#define ANDES_VENDOR_ID 0x31e #define ANDES_VENDOR_ID 0x31e
#define MICROCHIP_VENDOR_ID 0x029 #define MICROCHIP_VENDOR_ID 0x029
#define MIPS_VENDOR_ID 0x127
#define SIFIVE_VENDOR_ID 0x489 #define SIFIVE_VENDOR_ID 0x489
#define THEAD_VENDOR_ID 0x5b7 #define THEAD_VENDOR_ID 0x5b7
#define MIPS_VENDOR_ID 0x722
#endif #endif