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drm/rp1: rp1-dsi: Put all register defines into order

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Put particularly the PHY registers into order, bitmasks
defined alongside the registers, and Use tabs for indentation.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
This commit is contained in:
Dave Stevenson
2025-09-25 14:09:55 +01:00
committed by Dom Cobley
parent 14e1518f33
commit 95d366ec5d
1 changed files with 123 additions and 134 deletions
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95
drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c
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@@ -27,9 +27,22 @@
#define DSI_DBI_PARTITIONING_EN 0x024
#define DSI_DBI_CMDSIZE 0x028
#define DSI_PCKHDL_CFG 0x02C
#define DSI_PCKHDL_EOTP_TX_EN BIT(0)
#define DSI_PCKHDL_BTA_EN BIT(2)
#define DSI_GEN_VCID 0x030
#define DSI_MODE_CFG 0x034
#define DSI_VID_MODE_CFG 0x038
#define DSI_VID_MODE_LP_CMD_EN BIT(15)
#define DSI_VID_MODE_FRAME_BTA_ACK_EN BIT(14)
#define DSI_VID_MODE_LP_HFP_EN BIT(13)
#define DSI_VID_MODE_LP_HBP_EN BIT(12)
#define DSI_VID_MODE_LP_VACT_EN BIT(11)
#define DSI_VID_MODE_LP_VFP_EN BIT(10)
#define DSI_VID_MODE_LP_VBP_EN BIT(9)
#define DSI_VID_MODE_LP_VSA_EN BIT(8)
#define DSI_VID_MODE_SYNC_PULSES 0
#define DSI_VID_MODE_SYNC_EVENTS 1
#define DSI_VID_MODE_BURST 2
#define DSI_VID_PKT_SIZE 0x03C
#define DSI_VID_NUM_CHUNKS 0x040
#define DSI_VID_NULL_SIZE 0x044
@@ -42,6 +55,8 @@
#define DSI_VID_VACTIVE_LINES 0x060
#define DSI_EDPI_CMD_SIZE 0x064
#define DSI_CMD_MODE_CFG 0x068
#define DSI_CMD_MODE_ALL_LP 0x10f7f00
#define DSI_CMD_MODE_ACK_RQST_EN BIT(1)
#define DSI_GEN_HDR 0x06C
#define DSI_GEN_PLD_DATA 0x070
#define DSI_CMD_PKT_STATUS 0x074
@@ -54,18 +69,36 @@
#define DSI_SDF_3D 0x090
#define DSI_LPCLK_CTRL 0x094
#define DSI_PHY_TMR_LPCLK_CFG 0x098
#define DSI_PHY_TMR_HS2LP_LSB 16
#define DSI_PHY_TMR_LP2HS_LSB 0
#define DSI_PHY_TMR_HS2LP_LSB 16
#define DSI_PHY_TMR_LP2HS_LSB 0
#define DSI_PHY_TMR_CFG 0x09C
#define DSI_PHY_TMR_RD_CFG 0x0F4
#define DSI_PHYRSTZ 0x0A0
#define DSI_PHYRSTZ_SHUTDOWNZ_LSB 0
#define DSI_PHYRSTZ_SHUTDOWNZ_BITS BIT(DSI_PHYRSTZ_SHUTDOWNZ_LSB)
#define DSI_PHYRSTZ_RSTZ_LSB 1
#define DSI_PHYRSTZ_RSTZ_BITS BIT(DSI_PHYRSTZ_RSTZ_LSB)
#define DSI_PHYRSTZ_ENABLECLK_LSB 2
#define DSI_PHYRSTZ_ENABLECLK_BITS BIT(DSI_PHYRSTZ_ENABLECLK_LSB)
#define DSI_PHYRSTZ_FORCEPLL_LSB 3
#define DSI_PHYRSTZ_FORCEPLL_BITS BIT(DSI_PHYRSTZ_FORCEPLL_LSB)
#define DSI_PHY_IF_CFG 0x0A4
#define DSI_PHY_ULPS_CTRL 0x0A8
#define DSI_PHY_TX_TRIGGERS 0x0AC
#define DSI_PHY_STATUS 0x0B0
#define DSI_PHY_TST_CTRL0 0x0B4
#define DPHY_CTRL0_PHY_TESTCLK_LSB 1
#define DPHY_CTRL0_PHY_TESTCLK_BITS BIT(DPHY_CTRL0_PHY_TESTCLK_LSB)
#define DPHY_CTRL0_PHY_TESTCLR_LSB 0
#define DPHY_CTRL0_PHY_TESTCLR_BITS BIT(DPHY_CTRL0_PHY_TESTCLR_LSB)
#define DSI_PHY_TST_CTRL1 0x0B8
#define DPHY_CTRL1_PHY_TESTDIN_LSB 0
#define DPHY_CTRL1_PHY_TESTDIN_BITS (0xff << DPHY_CTRL1_PHY_TESTDIN_LSB)
#define DPHY_CTRL1_PHY_TESTDOUT_LSB 8
#define DPHY_CTRL1_PHY_TESTDOUT_BITS (0xff << DPHY_CTRL1_PHY_TESTDOUT_LSB)
#define DPHY_CTRL1_PHY_TESTEN_LSB 16
#define DPHY_CTRL1_PHY_TESTEN_BITS BIT(DPHY_CTRL1_PHY_TESTEN_LSB)
#define DSI_INT_ST0 0x0BC
#define DSI_INT_ST1 0x0C0
#define DSI_INT_MASK0_CFG 0x0C4
@@ -101,61 +134,17 @@
#define DSI_DSC_PARAMETER 0x0F0
/* And some bitfield definitions */
#define DSI_PCKHDL_EOTP_TX_EN BIT(0)
#define DSI_PCKHDL_BTA_EN BIT(2)
#define DSI_VID_MODE_LP_CMD_EN BIT(15)
#define DSI_VID_MODE_FRAME_BTA_ACK_EN BIT(14)
#define DSI_VID_MODE_LP_HFP_EN BIT(13)
#define DSI_VID_MODE_LP_HBP_EN BIT(12)
#define DSI_VID_MODE_LP_VACT_EN BIT(11)
#define DSI_VID_MODE_LP_VFP_EN BIT(10)
#define DSI_VID_MODE_LP_VBP_EN BIT(9)
#define DSI_VID_MODE_LP_VSA_EN BIT(8)
#define DSI_VID_MODE_SYNC_PULSES 0
#define DSI_VID_MODE_SYNC_EVENTS 1
#define DSI_VID_MODE_BURST 2
#define DSI_CMD_MODE_ALL_LP 0x10f7f00
#define DSI_CMD_MODE_ACK_RQST_EN BIT(1)
#define DPHY_PWR_UP_SHUTDOWNZ_LSB 0
#define DPHY_PWR_UP_SHUTDOWNZ_BITS BIT(DPHY_PWR_UP_SHUTDOWNZ_LSB)
#define DPHY_CTRL0_PHY_TESTCLK_LSB 1
#define DPHY_CTRL0_PHY_TESTCLK_BITS BIT(DPHY_CTRL0_PHY_TESTCLK_LSB)
#define DPHY_CTRL0_PHY_TESTCLR_LSB 0
#define DPHY_CTRL0_PHY_TESTCLR_BITS BIT(DPHY_CTRL0_PHY_TESTCLR_LSB)
#define DPHY_CTRL1_PHY_TESTDIN_LSB 0
#define DPHY_CTRL1_PHY_TESTDIN_BITS (0xff << DPHY_CTRL1_PHY_TESTDIN_LSB)
#define DPHY_CTRL1_PHY_TESTDOUT_LSB 8
#define DPHY_CTRL1_PHY_TESTDOUT_BITS (0xff << DPHY_CTRL1_PHY_TESTDOUT_LSB)
#define DPHY_CTRL1_PHY_TESTEN_LSB 16
#define DPHY_CTRL1_PHY_TESTEN_BITS BIT(DPHY_CTRL1_PHY_TESTEN_LSB)
#define DSI_PHYRSTZ_SHUTDOWNZ_LSB 0
#define DSI_PHYRSTZ_SHUTDOWNZ_BITS BIT(DSI_PHYRSTZ_SHUTDOWNZ_LSB)
#define DSI_PHYRSTZ_RSTZ_LSB 1
#define DSI_PHYRSTZ_RSTZ_BITS BIT(DSI_PHYRSTZ_RSTZ_LSB)
#define DSI_PHYRSTZ_ENABLECLK_LSB 2
#define DSI_PHYRSTZ_ENABLECLK_BITS BIT(DSI_PHYRSTZ_ENABLECLK_LSB)
#define DSI_PHYRSTZ_FORCEPLL_LSB 3
#define DSI_PHYRSTZ_FORCEPLL_BITS BIT(DSI_PHYRSTZ_FORCEPLL_LSB)
#define DPHY_HS_RX_CTRL_LANE0_OFFSET 0x44
/* PHY "test and control mode" registers */
#define DPHY_PLL_BIAS_OFFSET 0x10
#define DPHY_PLL_BIAS_VCO_RANGE_LSB 3
#define DPHY_PLL_BIAS_USE_PROGRAMMED_VCO_RANGE BIT(7)
#define DPHY_PLL_CHARGE_PUMP_OFFSET 0x11
#define DPHY_PLL_LPF_OFFSET 0x12
#define DPHY_PLL_INPUT_DIV_OFFSET 0x17
#define DPHY_PLL_LOOP_DIV_OFFSET 0x18
#define DPHY_PLL_DIV_CTRL_OFFSET 0x19
#define DPHY_HS_RX_CTRL_LANE0_OFFSET 0x44
#define DPHY_PLL_BIAS_OFFSET 0x10
#define DPHY_PLL_BIAS_VCO_RANGE_LSB 3
#define DPHY_PLL_BIAS_USE_PROGRAMMED_VCO_RANGE BIT(7)
#define DPHY_PLL_CHARGE_PUMP_OFFSET 0x11
#define DPHY_PLL_LPF_OFFSET 0x12
#define DSI_WRITE(reg, val) writel((val), dsi->hw_base[RP1DSI_HW_BLOCK_DSI] + (reg))
#define DSI_READ(reg) readl(dsi->hw_base[RP1DSI_HW_BLOCK_DSI] + (reg))