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radeon: insert 10ms sleep in dce5_crtc_load_lut

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[ Upstream commit ec3d65082d ]

Per at least one tester this is enough magic to recover the regression
introduced for some people (but not all) in

commit b8e2b0199c
Author: Peter Rosin <peda@axentia.se>
Date:   Tue Jul 4 12:36:57 2017 +0200

    drm/fb-helper: factor out pseudo-palette

which for radeon had the side-effect of refactoring out a seemingly
redudant writing of the color palette.

10ms in a fairly slow modeset path feels like an acceptable form of
duct-tape, so maybe worth a shot and see what sticks.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
References: https://bugzilla.kernel.org/show_bug.cgi?id=198123
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Daniel Vetter
2020-01-28 17:09:52 +01:00
committed by Greg Kroah-Hartman
parent 1432928883
commit 9d7222c9f9
1 changed files with 2 additions and 0 deletions
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2
drivers/gpu/drm/radeon/radeon_display.c
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@@ -127,6 +127,8 @@ static void dce5_crtc_load_lut(struct drm_crtc *crtc)
DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
msleep(10);
WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
(NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));