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MIPS: mscc: ocelot: fix length of memory address space for MIIM

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[ Upstream commit 49e5bb13ad ]

The length of memory address space for MIIM0 is from 0x7107009c to
0x710700bf included which is 36 bytes long in decimal, or 0x24 bytes in
hexadecimal and not 0x36.

Fixes: 49b031690a ("MIPS: mscc: Add switch to ocelot")

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20013/
Cc: robh+dt@kernel.org
Cc: mark.rutland@arm.com
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Quentin Schulz
2018-07-25 14:21:32 +02:00
committed by Greg Kroah-Hartman
parent 20452f8f04
commit 9daa1d751d
1 changed files with 1 additions and 1 deletions
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2
arch/mips/boot/dts/mscc/ocelot.dtsi
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@@ -184,7 +184,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "mscc,ocelot-miim"; compatible = "mscc,ocelot-miim";
reg = <0x107009c 0x36>, <0x10700f0 0x8>; reg = <0x107009c 0x24>, <0x10700f0 0x8>;
interrupts = <14>; interrupts = <14>;
status = "disabled"; status = "disabled";