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drm/rp1: rp1-dsi: Remove all the unused boilerplate register defines
There was lots of register definition information dumped from the some source into the driver but unused. Remove it, and format the remaining lines according to the Linux kernel coding style. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
This commit is contained in:
Dave Stevenson
committed by
Dom Cobley
Dom Cobley
parent
98082fd92c
commit
9df1624906
@@ -146,959 +146,34 @@
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#define DPHY_HS_RX_CTRL_LANE0_OFFSET 0x44
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#define DSI_WRITE(reg, val) writel((val), dsi->hw_base[RP1DSI_HW_BLOCK_DSI] + (reg))
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#define DSI_READ(reg) readl(dsi->hw_base[RP1DSI_HW_BLOCK_DSI] + (reg))
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#define DSI_WRITE(reg, val) writel((val), dsi->hw_base[RP1DSI_HW_BLOCK_DSI] + (reg))
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#define DSI_READ(reg) readl(dsi->hw_base[RP1DSI_HW_BLOCK_DSI] + (reg))
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// ================================================================================
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// Register block : RPI_MIPICFG
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// Version : 1
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// Bus type : apb
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// Description : Register block to control mipi DPHY
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// ================================================================================
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#define RPI_MIPICFG_REGS_RWTYPE_MSB 13
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#define RPI_MIPICFG_REGS_RWTYPE_LSB 12
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// ================================================================================
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// Register : RPI_MIPICFG_CLK2FC
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// JTAG access : synchronous
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// Description : None
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#define RPI_MIPICFG_CLK2FC_OFFSET 0x00000000
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#define RPI_MIPICFG_CLK2FC_BITS 0x00000007
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#define RPI_MIPICFG_CLK2FC_RESET 0x00000000
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_CLK2FC_SEL
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// Description : select a clock to be sent to the frequency counter
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// 7 = none
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// 6 = none
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// 5 = none
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// 4 = rxbyteclkhs (187.5MHz)
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// 3 = rxclkesc0 (20MHz)
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// 2 = txbyteclkhs (187.5MHz)
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// 1 = txclkesc (125MHz)
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// 0 = none
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#define RPI_MIPICFG_CLK2FC_SEL_RESET 0x0
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#define RPI_MIPICFG_CLK2FC_SEL_BITS 0x00000007
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#define RPI_MIPICFG_CLK2FC_SEL_MSB 2
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#define RPI_MIPICFG_CLK2FC_SEL_LSB 0
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#define RPI_MIPICFG_CLK2FC_SEL_ACCESS "RW"
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// ================================================================================
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// Register : RPI_MIPICFG_CFG
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// JTAG access : asynchronous
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// Description : Top level configuration
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#define RPI_MIPICFG_CFG_OFFSET 0x00000004
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#define RPI_MIPICFG_CFG_BITS 0x00000111
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#define RPI_MIPICFG_CFG_RESET 0x00000001
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_CFG_DPIUPDATE
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// Description : Indicate the DSI block that the next frame will have a new video configuration
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#define RPI_MIPICFG_CFG_DPIUPDATE_RESET 0x0
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#define RPI_MIPICFG_CFG_DPIUPDATE_BITS 0x00000100
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#define RPI_MIPICFG_CFG_DPIUPDATE_MSB 8
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#define RPI_MIPICFG_CFG_DPIUPDATE_LSB 8
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#define RPI_MIPICFG_CFG_DPIUPDATE_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_CFG_SEL_TE_EXT
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// Description : Select the TE source: 1 - ext, 0 - int
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#define RPI_MIPICFG_CFG_SEL_TE_EXT_RESET 0x0
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#define RPI_MIPICFG_CFG_SEL_TE_EXT_BITS 0x00000010
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#define RPI_MIPICFG_CFG_SEL_TE_EXT_MSB 4
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#define RPI_MIPICFG_CFG_SEL_TE_EXT_LSB 4
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#define RPI_MIPICFG_CFG_SEL_TE_EXT_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_CFG_SEL_CSI_DSI_N
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// Description : Select PHY direction: input to CSI, output from DSI. CSI 1 DSI 0
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#define RPI_MIPICFG_CFG_SEL_CSI_DSI_N_RESET 0x1
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#define RPI_MIPICFG_CFG_SEL_CSI_DSI_N_BITS 0x00000001
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#define RPI_MIPICFG_CFG_SEL_CSI_DSI_N_MSB 0
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#define RPI_MIPICFG_CFG_SEL_CSI_DSI_N_LSB 0
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#define RPI_MIPICFG_CFG_SEL_CSI_DSI_N_ACCESS "RW"
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// ================================================================================
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// Register : RPI_MIPICFG_TE
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// JTAG access : synchronous
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// Description : Tearing effect processing
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#define RPI_MIPICFG_TE_OFFSET 0x00000008
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#define RPI_MIPICFG_TE_BITS 0x10ffffff
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#define RPI_MIPICFG_TE_RESET 0x00000000
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_TE_ARM
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// Description : Tearing effect arm
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#define RPI_MIPICFG_TE_ARM_RESET 0x0
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#define RPI_MIPICFG_TE_ARM_BITS 0x10000000
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#define RPI_MIPICFG_TE_ARM_MSB 28
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#define RPI_MIPICFG_TE_ARM_LSB 28
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#define RPI_MIPICFG_TE_ARM_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_TE_HALT_CYC
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// Description : When arm pulse has been seen, wait for te; then halt the dpi block
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// for this many clk_dpi cycles
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#define RPI_MIPICFG_TE_HALT_CYC_RESET 0x000000
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#define RPI_MIPICFG_TE_HALT_CYC_BITS 0x00ffffff
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#define RPI_MIPICFG_TE_HALT_CYC_MSB 23
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#define RPI_MIPICFG_TE_HALT_CYC_LSB 0
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#define RPI_MIPICFG_TE_HALT_CYC_ACCESS "RW"
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// ================================================================================
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// Register : RPI_MIPICFG_DPHY_MONITOR
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// JTAG access : asynchronous
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// Description : DPHY status monitors for analog DFT
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#define RPI_MIPICFG_DPHY_MONITOR_OFFSET 0x00000010
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#define RPI_MIPICFG_DPHY_MONITOR_BITS 0x00111fff
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#define RPI_MIPICFG_DPHY_MONITOR_RESET 0x00000000
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_MONITOR_LOCK
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// Description : None
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#define RPI_MIPICFG_DPHY_MONITOR_LOCK_RESET 0x0
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#define RPI_MIPICFG_DPHY_MONITOR_LOCK_BITS 0x00100000
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#define RPI_MIPICFG_DPHY_MONITOR_LOCK_MSB 20
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#define RPI_MIPICFG_DPHY_MONITOR_LOCK_LSB 20
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#define RPI_MIPICFG_DPHY_MONITOR_LOCK_ACCESS "RO"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_MONITOR_BISTOK
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// Description : None
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#define RPI_MIPICFG_DPHY_MONITOR_BISTOK_RESET 0x0
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#define RPI_MIPICFG_DPHY_MONITOR_BISTOK_BITS 0x00010000
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#define RPI_MIPICFG_DPHY_MONITOR_BISTOK_MSB 16
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#define RPI_MIPICFG_DPHY_MONITOR_BISTOK_LSB 16
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#define RPI_MIPICFG_DPHY_MONITOR_BISTOK_ACCESS "RO"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_MONITOR_STOPSTATECLK
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// Description : None
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#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATECLK_RESET 0x0
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#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATECLK_BITS 0x00001000
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#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATECLK_MSB 12
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#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATECLK_LSB 12
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#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATECLK_ACCESS "RO"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_MONITOR_STOPSTATEDATA
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// Description : None
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#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATEDATA_RESET 0x0
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#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATEDATA_BITS 0x00000f00
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#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATEDATA_MSB 11
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#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATEDATA_LSB 8
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#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATEDATA_ACCESS "RO"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_MONITOR_TESTDOUT
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// Description : None
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#define RPI_MIPICFG_DPHY_MONITOR_TESTDOUT_RESET 0x00
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#define RPI_MIPICFG_DPHY_MONITOR_TESTDOUT_BITS 0x000000ff
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#define RPI_MIPICFG_DPHY_MONITOR_TESTDOUT_MSB 7
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#define RPI_MIPICFG_DPHY_MONITOR_TESTDOUT_LSB 0
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#define RPI_MIPICFG_DPHY_MONITOR_TESTDOUT_ACCESS "RO"
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// ================================================================================
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// Register : RPI_MIPICFG_DPHY_CTRL_0
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// JTAG access : asynchronous
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// Description : DPHY control for analog DFT
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#define RPI_MIPICFG_DPHY_CTRL_0_OFFSET 0x00000014
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#define RPI_MIPICFG_DPHY_CTRL_0_BITS 0x0000003f
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#define RPI_MIPICFG_DPHY_CTRL_0_RESET 0x00000000
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_CTRL_0_TEST_LPMODE
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// Description : When set in lpmode, TXCLKESC is driven from clk_vec(driven from clocks block)
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#define RPI_MIPICFG_DPHY_CTRL_0_TEST_LPMODE_RESET 0x0
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#define RPI_MIPICFG_DPHY_CTRL_0_TEST_LPMODE_BITS 0x00000020
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#define RPI_MIPICFG_DPHY_CTRL_0_TEST_LPMODE_MSB 5
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#define RPI_MIPICFG_DPHY_CTRL_0_TEST_LPMODE_LSB 5
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#define RPI_MIPICFG_DPHY_CTRL_0_TEST_LPMODE_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_CTRL_0_TEST_ENA
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// Description : When set, drive the DPHY from the test registers
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#define RPI_MIPICFG_DPHY_CTRL_0_TEST_ENA_RESET 0x0
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#define RPI_MIPICFG_DPHY_CTRL_0_TEST_ENA_BITS 0x00000010
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#define RPI_MIPICFG_DPHY_CTRL_0_TEST_ENA_MSB 4
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#define RPI_MIPICFG_DPHY_CTRL_0_TEST_ENA_LSB 4
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#define RPI_MIPICFG_DPHY_CTRL_0_TEST_ENA_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_CTRL_0_CFG_CLK_DIS
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// Description : When test_ena is set, disable cfg_clk
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#define RPI_MIPICFG_DPHY_CTRL_0_CFG_CLK_DIS_RESET 0x0
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#define RPI_MIPICFG_DPHY_CTRL_0_CFG_CLK_DIS_BITS 0x00000008
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#define RPI_MIPICFG_DPHY_CTRL_0_CFG_CLK_DIS_MSB 3
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#define RPI_MIPICFG_DPHY_CTRL_0_CFG_CLK_DIS_LSB 3
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#define RPI_MIPICFG_DPHY_CTRL_0_CFG_CLK_DIS_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_CTRL_0_REFCLK_DIS
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// Description : When test_ena is set, disable refclk
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#define RPI_MIPICFG_DPHY_CTRL_0_REFCLK_DIS_RESET 0x0
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#define RPI_MIPICFG_DPHY_CTRL_0_REFCLK_DIS_BITS 0x00000004
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#define RPI_MIPICFG_DPHY_CTRL_0_REFCLK_DIS_MSB 2
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#define RPI_MIPICFG_DPHY_CTRL_0_REFCLK_DIS_LSB 2
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#define RPI_MIPICFG_DPHY_CTRL_0_REFCLK_DIS_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_CTRL_0_TXCLKESC_DIS
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// Description : When test_ena is set, disable txclkesc
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#define RPI_MIPICFG_DPHY_CTRL_0_TXCLKESC_DIS_RESET 0x0
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#define RPI_MIPICFG_DPHY_CTRL_0_TXCLKESC_DIS_BITS 0x00000002
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#define RPI_MIPICFG_DPHY_CTRL_0_TXCLKESC_DIS_MSB 1
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#define RPI_MIPICFG_DPHY_CTRL_0_TXCLKESC_DIS_LSB 1
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#define RPI_MIPICFG_DPHY_CTRL_0_TXCLKESC_DIS_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_CTRL_0_TXBYTECLKHS_DIS
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// Description : When test_ena is set, disable txbyteclkhs
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#define RPI_MIPICFG_DPHY_CTRL_0_TXBYTECLKHS_DIS_RESET 0x0
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#define RPI_MIPICFG_DPHY_CTRL_0_TXBYTECLKHS_DIS_BITS 0x00000001
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#define RPI_MIPICFG_DPHY_CTRL_0_TXBYTECLKHS_DIS_MSB 0
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#define RPI_MIPICFG_DPHY_CTRL_0_TXBYTECLKHS_DIS_LSB 0
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#define RPI_MIPICFG_DPHY_CTRL_0_TXBYTECLKHS_DIS_ACCESS "RW"
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// ================================================================================
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// Register : RPI_MIPICFG_DPHY_CTRL_1
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// JTAG access : asynchronous
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// Description : DPHY control for analog DFT
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#define RPI_MIPICFG_DPHY_CTRL_1_OFFSET 0x00000018
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#define RPI_MIPICFG_DPHY_CTRL_1_BITS 0x7fffffff
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#define RPI_MIPICFG_DPHY_CTRL_1_RESET 0x00000000
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_CTRL_1_FORCEPLL
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// Description : None
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#define RPI_MIPICFG_DPHY_CTRL_1_FORCEPLL_RESET 0x0
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#define RPI_MIPICFG_DPHY_CTRL_1_FORCEPLL_BITS 0x40000000
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#define RPI_MIPICFG_DPHY_CTRL_1_FORCEPLL_MSB 30
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#define RPI_MIPICFG_DPHY_CTRL_1_FORCEPLL_LSB 30
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#define RPI_MIPICFG_DPHY_CTRL_1_FORCEPLL_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_CTRL_1_SHUTDOWNZ
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// Description : None
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#define RPI_MIPICFG_DPHY_CTRL_1_SHUTDOWNZ_RESET 0x0
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#define RPI_MIPICFG_DPHY_CTRL_1_SHUTDOWNZ_BITS 0x20000000
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#define RPI_MIPICFG_DPHY_CTRL_1_SHUTDOWNZ_MSB 29
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#define RPI_MIPICFG_DPHY_CTRL_1_SHUTDOWNZ_LSB 29
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#define RPI_MIPICFG_DPHY_CTRL_1_SHUTDOWNZ_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_CTRL_1_RSTZ
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// Description : None
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#define RPI_MIPICFG_DPHY_CTRL_1_RSTZ_RESET 0x0
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#define RPI_MIPICFG_DPHY_CTRL_1_RSTZ_BITS 0x10000000
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#define RPI_MIPICFG_DPHY_CTRL_1_RSTZ_MSB 28
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#define RPI_MIPICFG_DPHY_CTRL_1_RSTZ_LSB 28
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#define RPI_MIPICFG_DPHY_CTRL_1_RSTZ_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_CTRL_1_MASTERSLAVEZ
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// Description : None
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#define RPI_MIPICFG_DPHY_CTRL_1_MASTERSLAVEZ_RESET 0x0
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#define RPI_MIPICFG_DPHY_CTRL_1_MASTERSLAVEZ_BITS 0x08000000
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#define RPI_MIPICFG_DPHY_CTRL_1_MASTERSLAVEZ_MSB 27
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#define RPI_MIPICFG_DPHY_CTRL_1_MASTERSLAVEZ_LSB 27
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#define RPI_MIPICFG_DPHY_CTRL_1_MASTERSLAVEZ_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_CTRL_1_BISTON
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// Description : None
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#define RPI_MIPICFG_DPHY_CTRL_1_BISTON_RESET 0x0
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#define RPI_MIPICFG_DPHY_CTRL_1_BISTON_BITS 0x04000000
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#define RPI_MIPICFG_DPHY_CTRL_1_BISTON_MSB 26
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#define RPI_MIPICFG_DPHY_CTRL_1_BISTON_LSB 26
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#define RPI_MIPICFG_DPHY_CTRL_1_BISTON_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTHSCLK
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// Description : None
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#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTHSCLK_RESET 0x0
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#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTHSCLK_BITS 0x02000000
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#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTHSCLK_MSB 25
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#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTHSCLK_LSB 25
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#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTHSCLK_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_CTRL_1_ENABLECLK
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// Description : None
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLECLK_RESET 0x0
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLECLK_BITS 0x01000000
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLECLK_MSB 24
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLECLK_LSB 24
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLECLK_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_CTRL_1_ENABLE_3
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// Description : None
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_3_RESET 0x0
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_3_BITS 0x00800000
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_3_MSB 23
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_3_LSB 23
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_3_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_CTRL_1_ENABLE_2
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// Description : None
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_2_RESET 0x0
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_2_BITS 0x00400000
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_2_MSB 22
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_2_LSB 22
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_2_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_CTRL_1_ENABLE_1
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// Description : None
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_1_RESET 0x0
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_1_BITS 0x00200000
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_1_MSB 21
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_1_LSB 21
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_1_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_CTRL_1_ENABLE_0
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// Description : None
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_0_RESET 0x0
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_0_BITS 0x00100000
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_0_MSB 20
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_0_LSB 20
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#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_0_ACCESS "RW"
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// --------------------------------------------------------------------------------
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// Field : RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_3
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// Description : None
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#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_3_RESET 0x0
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#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_3_BITS 0x00080000
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#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_3_MSB 19
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_3_LSB 19
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_3_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_2
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_2_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_2_BITS 0x00040000
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_2_MSB 18
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_2_LSB 18
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_2_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_1
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_1_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_1_BITS 0x00020000
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_1_MSB 17
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_1_LSB 17
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_1_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_0
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_0_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_0_BITS 0x00010000
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_0_MSB 16
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_0_LSB 16
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_0_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_3
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_3_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_3_BITS 0x00008000
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_3_MSB 15
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_3_LSB 15
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_3_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_2
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_2_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_2_BITS 0x00004000
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_2_MSB 14
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_2_LSB 14
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_2_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_1
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_1_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_1_BITS 0x00002000
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_1_MSB 13
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_1_LSB 13
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_1_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_0
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_0_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_0_BITS 0x00001000
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_0_MSB 12
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_0_LSB 12
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_0_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_3
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_3_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_3_BITS 0x00000800
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_3_MSB 11
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_3_LSB 11
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_3_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_2
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_2_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_2_BITS 0x00000400
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_2_MSB 10
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_2_LSB 10
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_2_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_1
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_1_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_1_BITS 0x00000200
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_1_MSB 9
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_1_LSB 9
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_1_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_0
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_0_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_0_BITS 0x00000100
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_0_MSB 8
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_0_LSB 8
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_0_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_3
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_3_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_3_BITS 0x00000080
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_3_MSB 7
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_3_LSB 7
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_3_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_2
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_2_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_2_BITS 0x00000040
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_2_MSB 6
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_2_LSB 6
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_2_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_1
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_1_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_1_BITS 0x00000020
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_1_MSB 5
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_1_LSB 5
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_1_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_0
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_0_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_0_BITS 0x00000010
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_0_MSB 4
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_0_LSB 4
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_0_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_3
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_3_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_3_BITS 0x00000008
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_3_MSB 3
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_3_LSB 3
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_3_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_2
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_2_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_2_BITS 0x00000004
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_2_MSB 2
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_2_LSB 2
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_2_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_1
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_1_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_1_BITS 0x00000002
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_1_MSB 1
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_1_LSB 1
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_1_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_0
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_0_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_0_BITS 0x00000001
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_0_MSB 0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_0_LSB 0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_0_ACCESS "RW"
|
||||
// ================================================================================
|
||||
// Register : RPI_MIPICFG_DPHY_CTRL_2
|
||||
// JTAG access : asynchronous
|
||||
// Description : DPHY control for analog DFT
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_OFFSET 0x0000001c
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_BITS 0x000007ff
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_RESET 0x00000000
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_2_TESTCLK
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLK_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLK_BITS 0x00000400
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLK_MSB 10
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLK_LSB 10
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLK_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_2_TESTEN
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTEN_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTEN_BITS 0x00000200
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTEN_MSB 9
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTEN_LSB 9
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTEN_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_2_TESTCLR
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLR_RESET 0x0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLR_BITS 0x00000100
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLR_MSB 8
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLR_LSB 8
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLR_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_2_TESTDIN
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTDIN_RESET 0x00
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTDIN_BITS 0x000000ff
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTDIN_MSB 7
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTDIN_LSB 0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_TESTDIN_ACCESS "RW"
|
||||
// ================================================================================
|
||||
// Register : RPI_MIPICFG_DPHY_CTRL_3
|
||||
// JTAG access : asynchronous
|
||||
// Description : DPHY control for analog DFT
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_OFFSET 0x00000020
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_BITS 0xffffffff
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_RESET 0x00000000
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_3
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_3_RESET 0x00
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_3_BITS 0xff000000
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_3_MSB 31
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_3_LSB 24
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_3_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_2
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_2_RESET 0x00
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_2_BITS 0x00ff0000
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_2_MSB 23
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_2_LSB 16
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_2_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_1
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_1_RESET 0x00
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_1_BITS 0x0000ff00
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_1_MSB 15
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_1_LSB 8
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_1_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_0
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_0_RESET 0x00
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_0_BITS 0x000000ff
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_0_MSB 7
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_0_LSB 0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_0_ACCESS "RW"
|
||||
// ================================================================================
|
||||
// Register : RPI_MIPICFG_DPHY_CTRL_4
|
||||
// JTAG access : asynchronous
|
||||
// Description : DPHY control for analog DFT
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_OFFSET 0x00000024
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_BITS 0xffffffff
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_RESET 0x00000000
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_3
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_3_RESET 0x00
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_3_BITS 0xff000000
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_3_MSB 31
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_3_LSB 24
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_3_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_2
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_2_RESET 0x00
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_2_BITS 0x00ff0000
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_2_MSB 23
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_2_LSB 16
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_2_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_1
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_1_RESET 0x00
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_1_BITS 0x0000ff00
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_1_MSB 15
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_1_LSB 8
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_1_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_0
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_0_RESET 0x00
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_0_BITS 0x000000ff
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_0_MSB 7
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_0_LSB 0
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_0_ACCESS "RW"
|
||||
// ================================================================================
|
||||
// Register : RPI_MIPICFG_INTR
|
||||
// JTAG access : synchronous
|
||||
// Description : Raw Interrupts
|
||||
#define RPI_MIPICFG_INTR_OFFSET 0x00000028
|
||||
#define RPI_MIPICFG_INTR_BITS 0x0000000f
|
||||
#define RPI_MIPICFG_INTR_RESET 0x00000000
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_INTR_DSI_HOST
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_INTR_DSI_HOST_RESET 0x0
|
||||
#define RPI_MIPICFG_INTR_DSI_HOST_BITS 0x00000008
|
||||
#define RPI_MIPICFG_INTR_DSI_HOST_MSB 3
|
||||
#define RPI_MIPICFG_INTR_DSI_HOST_LSB 3
|
||||
#define RPI_MIPICFG_INTR_DSI_HOST_ACCESS "RO"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_INTR_CSI_HOST
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_INTR_CSI_HOST_RESET 0x0
|
||||
#define RPI_MIPICFG_INTR_CSI_HOST_BITS 0x00000004
|
||||
#define RPI_MIPICFG_INTR_CSI_HOST_MSB 2
|
||||
#define RPI_MIPICFG_INTR_CSI_HOST_LSB 2
|
||||
#define RPI_MIPICFG_INTR_CSI_HOST_ACCESS "RO"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_INTR_DSI_DMA
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_INTR_DSI_DMA_RESET 0x0
|
||||
#define RPI_MIPICFG_INTR_DSI_DMA_BITS 0x00000002
|
||||
#define RPI_MIPICFG_INTR_DSI_DMA_MSB 1
|
||||
#define RPI_MIPICFG_INTR_DSI_DMA_LSB 1
|
||||
#define RPI_MIPICFG_INTR_DSI_DMA_ACCESS "RO"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_INTR_CSI_DMA
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_INTR_CSI_DMA_RESET 0x0
|
||||
#define RPI_MIPICFG_INTR_CSI_DMA_BITS 0x00000001
|
||||
#define RPI_MIPICFG_INTR_CSI_DMA_MSB 0
|
||||
#define RPI_MIPICFG_INTR_CSI_DMA_LSB 0
|
||||
#define RPI_MIPICFG_INTR_CSI_DMA_ACCESS "RO"
|
||||
// ================================================================================
|
||||
// Register : RPI_MIPICFG_INTE
|
||||
// JTAG access : synchronous
|
||||
// Description : Interrupt Enable
|
||||
#define RPI_MIPICFG_INTE_OFFSET 0x0000002c
|
||||
#define RPI_MIPICFG_INTE_BITS 0x0000000f
|
||||
#define RPI_MIPICFG_INTE_RESET 0x00000000
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_INTE_DSI_HOST
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_INTE_DSI_HOST_RESET 0x0
|
||||
#define RPI_MIPICFG_INTE_DSI_HOST_BITS 0x00000008
|
||||
#define RPI_MIPICFG_INTE_DSI_HOST_MSB 3
|
||||
#define RPI_MIPICFG_INTE_DSI_HOST_LSB 3
|
||||
#define RPI_MIPICFG_INTE_DSI_HOST_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_INTE_CSI_HOST
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_INTE_CSI_HOST_RESET 0x0
|
||||
#define RPI_MIPICFG_INTE_CSI_HOST_BITS 0x00000004
|
||||
#define RPI_MIPICFG_INTE_CSI_HOST_MSB 2
|
||||
#define RPI_MIPICFG_INTE_CSI_HOST_LSB 2
|
||||
#define RPI_MIPICFG_INTE_CSI_HOST_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_INTE_DSI_DMA
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_INTE_DSI_DMA_RESET 0x0
|
||||
#define RPI_MIPICFG_INTE_DSI_DMA_BITS 0x00000002
|
||||
#define RPI_MIPICFG_INTE_DSI_DMA_MSB 1
|
||||
#define RPI_MIPICFG_INTE_DSI_DMA_LSB 1
|
||||
#define RPI_MIPICFG_INTE_DSI_DMA_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_INTE_CSI_DMA
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_INTE_CSI_DMA_RESET 0x0
|
||||
#define RPI_MIPICFG_INTE_CSI_DMA_BITS 0x00000001
|
||||
#define RPI_MIPICFG_INTE_CSI_DMA_MSB 0
|
||||
#define RPI_MIPICFG_INTE_CSI_DMA_LSB 0
|
||||
#define RPI_MIPICFG_INTE_CSI_DMA_ACCESS "RW"
|
||||
// ================================================================================
|
||||
// Register : RPI_MIPICFG_INTF
|
||||
// JTAG access : synchronous
|
||||
// Description : Interrupt Force
|
||||
#define RPI_MIPICFG_INTF_OFFSET 0x00000030
|
||||
#define RPI_MIPICFG_INTF_BITS 0x0000000f
|
||||
#define RPI_MIPICFG_INTF_RESET 0x00000000
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_INTF_DSI_HOST
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_INTF_DSI_HOST_RESET 0x0
|
||||
#define RPI_MIPICFG_INTF_DSI_HOST_BITS 0x00000008
|
||||
#define RPI_MIPICFG_INTF_DSI_HOST_MSB 3
|
||||
#define RPI_MIPICFG_INTF_DSI_HOST_LSB 3
|
||||
#define RPI_MIPICFG_INTF_DSI_HOST_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_INTF_CSI_HOST
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_INTF_CSI_HOST_RESET 0x0
|
||||
#define RPI_MIPICFG_INTF_CSI_HOST_BITS 0x00000004
|
||||
#define RPI_MIPICFG_INTF_CSI_HOST_MSB 2
|
||||
#define RPI_MIPICFG_INTF_CSI_HOST_LSB 2
|
||||
#define RPI_MIPICFG_INTF_CSI_HOST_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_INTF_DSI_DMA
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_INTF_DSI_DMA_RESET 0x0
|
||||
#define RPI_MIPICFG_INTF_DSI_DMA_BITS 0x00000002
|
||||
#define RPI_MIPICFG_INTF_DSI_DMA_MSB 1
|
||||
#define RPI_MIPICFG_INTF_DSI_DMA_LSB 1
|
||||
#define RPI_MIPICFG_INTF_DSI_DMA_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_INTF_CSI_DMA
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_INTF_CSI_DMA_RESET 0x0
|
||||
#define RPI_MIPICFG_INTF_CSI_DMA_BITS 0x00000001
|
||||
#define RPI_MIPICFG_INTF_CSI_DMA_MSB 0
|
||||
#define RPI_MIPICFG_INTF_CSI_DMA_LSB 0
|
||||
#define RPI_MIPICFG_INTF_CSI_DMA_ACCESS "RW"
|
||||
// ================================================================================
|
||||
// Register : RPI_MIPICFG_INTS
|
||||
// JTAG access : synchronous
|
||||
// Description : Interrupt status after masking & forcing
|
||||
#define RPI_MIPICFG_INTS_OFFSET 0x00000034
|
||||
#define RPI_MIPICFG_INTS_BITS 0x0000000f
|
||||
#define RPI_MIPICFG_INTS_RESET 0x00000000
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_INTS_DSI_HOST
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_INTS_DSI_HOST_RESET 0x0
|
||||
#define RPI_MIPICFG_INTS_DSI_HOST_BITS 0x00000008
|
||||
#define RPI_MIPICFG_INTS_DSI_HOST_MSB 3
|
||||
#define RPI_MIPICFG_INTS_DSI_HOST_LSB 3
|
||||
#define RPI_MIPICFG_INTS_DSI_HOST_ACCESS "RO"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_INTS_CSI_HOST
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_INTS_CSI_HOST_RESET 0x0
|
||||
#define RPI_MIPICFG_INTS_CSI_HOST_BITS 0x00000004
|
||||
#define RPI_MIPICFG_INTS_CSI_HOST_MSB 2
|
||||
#define RPI_MIPICFG_INTS_CSI_HOST_LSB 2
|
||||
#define RPI_MIPICFG_INTS_CSI_HOST_ACCESS "RO"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_INTS_DSI_DMA
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_INTS_DSI_DMA_RESET 0x0
|
||||
#define RPI_MIPICFG_INTS_DSI_DMA_BITS 0x00000002
|
||||
#define RPI_MIPICFG_INTS_DSI_DMA_MSB 1
|
||||
#define RPI_MIPICFG_INTS_DSI_DMA_LSB 1
|
||||
#define RPI_MIPICFG_INTS_DSI_DMA_ACCESS "RO"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_INTS_CSI_DMA
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_INTS_CSI_DMA_RESET 0x0
|
||||
#define RPI_MIPICFG_INTS_CSI_DMA_BITS 0x00000001
|
||||
#define RPI_MIPICFG_INTS_CSI_DMA_MSB 0
|
||||
#define RPI_MIPICFG_INTS_CSI_DMA_LSB 0
|
||||
#define RPI_MIPICFG_INTS_CSI_DMA_ACCESS "RO"
|
||||
// ================================================================================
|
||||
// Register : RPI_MIPICFG_BLOCK_ID
|
||||
// JTAG access : asynchronous
|
||||
// Description : Block Identifier
|
||||
#define RPI_MIPICFG_BLOCK_ID_OFFSET 0x00000038
|
||||
#define RPI_MIPICFG_BLOCK_ID_BITS 0xffffffff
|
||||
#define RPI_MIPICFG_BLOCK_ID_RESET 0x4d495049
|
||||
#define RPI_MIPICFG_BLOCK_ID_MSB 31
|
||||
#define RPI_MIPICFG_BLOCK_ID_LSB 0
|
||||
#define RPI_MIPICFG_BLOCK_ID_ACCESS "RO"
|
||||
// ================================================================================
|
||||
// Register : RPI_MIPICFG_INSTANCE_ID
|
||||
// JTAG access : asynchronous
|
||||
// Description : Block Instance Identifier
|
||||
#define RPI_MIPICFG_INSTANCE_ID_OFFSET 0x0000003c
|
||||
#define RPI_MIPICFG_INSTANCE_ID_BITS 0x0000000f
|
||||
#define RPI_MIPICFG_INSTANCE_ID_RESET 0x00000000
|
||||
#define RPI_MIPICFG_INSTANCE_ID_MSB 3
|
||||
#define RPI_MIPICFG_INSTANCE_ID_LSB 0
|
||||
#define RPI_MIPICFG_INSTANCE_ID_ACCESS "RO"
|
||||
// ================================================================================
|
||||
// Register : RPI_MIPICFG_RSTSEQ_AUTO
|
||||
// JTAG access : synchronous
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_OFFSET 0x00000040
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_BITS 0x00000007
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_RESET 0x00000007
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_RSTSEQ_AUTO_CSI
|
||||
// Description : 1 = reset is controlled by the sequencer
|
||||
// 0 = reset is controlled by rstseq_ctrl
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_CSI_RESET 0x1
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_CSI_BITS 0x00000004
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_CSI_MSB 2
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_CSI_LSB 2
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_CSI_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_RSTSEQ_AUTO_DPI
|
||||
// Description : 1 = reset is controlled by the sequencer
|
||||
// 0 = reset is controlled by rstseq_ctrl
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_DPI_RESET 0x1
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_DPI_BITS 0x00000002
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_DPI_MSB 1
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_DPI_LSB 1
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_DPI_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_RSTSEQ_AUTO_BUSADAPTER
|
||||
// Description : 1 = reset is controlled by the sequencer
|
||||
// 0 = reset is controlled by rstseq_ctrl
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_BUSADAPTER_RESET 0x1
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_BUSADAPTER_BITS 0x00000001
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_BUSADAPTER_MSB 0
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_BUSADAPTER_LSB 0
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_BUSADAPTER_ACCESS "RW"
|
||||
// ================================================================================
|
||||
// Register : RPI_MIPICFG_RSTSEQ_PARALLEL
|
||||
// JTAG access : synchronous
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_OFFSET 0x00000044
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_BITS 0x00000007
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_RESET 0x00000006
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_RSTSEQ_PARALLEL_CSI
|
||||
// Description : Is this reset parallel (i.e. not part of the sequence)
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_CSI_RESET 0x1
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_CSI_BITS 0x00000004
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_CSI_MSB 2
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_CSI_LSB 2
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_CSI_ACCESS "RO"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_RSTSEQ_PARALLEL_DPI
|
||||
// Description : Is this reset parallel (i.e. not part of the sequence)
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_DPI_RESET 0x1
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_DPI_BITS 0x00000002
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_DPI_MSB 1
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_DPI_LSB 1
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_DPI_ACCESS "RO"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_RSTSEQ_PARALLEL_BUSADAPTER
|
||||
// Description : Is this reset parallel (i.e. not part of the sequence)
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_BUSADAPTER_RESET 0x0
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_BUSADAPTER_BITS 0x00000001
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_BUSADAPTER_MSB 0
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_BUSADAPTER_LSB 0
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_BUSADAPTER_ACCESS "RO"
|
||||
// ================================================================================
|
||||
// Register : RPI_MIPICFG_RSTSEQ_CTRL
|
||||
// JTAG access : synchronous
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_OFFSET 0x00000048
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_BITS 0x00000007
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_RESET 0x00000000
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_RSTSEQ_CTRL_CSI
|
||||
// Description : 1 = keep the reset asserted
|
||||
// 0 = keep the reset deasserted
|
||||
// This is ignored if rstseq_auto=1
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_CSI_RESET 0x0
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_CSI_BITS 0x00000004
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_CSI_MSB 2
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_CSI_LSB 2
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_CSI_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_RSTSEQ_CTRL_DPI
|
||||
// Description : 1 = keep the reset asserted
|
||||
// 0 = keep the reset deasserted
|
||||
// This is ignored if rstseq_auto=1
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_DPI_RESET 0x0
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_DPI_BITS 0x00000002
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_DPI_MSB 1
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_DPI_LSB 1
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_DPI_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_RSTSEQ_CTRL_BUSADAPTER
|
||||
// Description : 1 = keep the reset asserted
|
||||
// 0 = keep the reset deasserted
|
||||
// This is ignored if rstseq_auto=1
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_BUSADAPTER_RESET 0x0
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_BUSADAPTER_BITS 0x00000001
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_BUSADAPTER_MSB 0
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_BUSADAPTER_LSB 0
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_BUSADAPTER_ACCESS "RW"
|
||||
// ================================================================================
|
||||
// Register : RPI_MIPICFG_RSTSEQ_TRIG
|
||||
// JTAG access : synchronous
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_OFFSET 0x0000004c
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_BITS 0x00000007
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_RESET 0x00000000
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_RSTSEQ_TRIG_CSI
|
||||
// Description : Pulses the reset output
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_CSI_RESET 0x0
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_CSI_BITS 0x00000004
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_CSI_MSB 2
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_CSI_LSB 2
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_CSI_ACCESS "SC"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_RSTSEQ_TRIG_DPI
|
||||
// Description : Pulses the reset output
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_DPI_RESET 0x0
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_DPI_BITS 0x00000002
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_DPI_MSB 1
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_DPI_LSB 1
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_DPI_ACCESS "SC"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_RSTSEQ_TRIG_BUSADAPTER
|
||||
// Description : Pulses the reset output
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_BUSADAPTER_RESET 0x0
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_BUSADAPTER_BITS 0x00000001
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_BUSADAPTER_MSB 0
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_BUSADAPTER_LSB 0
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_BUSADAPTER_ACCESS "SC"
|
||||
// ================================================================================
|
||||
// Register : RPI_MIPICFG_RSTSEQ_DONE
|
||||
// JTAG access : synchronous
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_OFFSET 0x00000050
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_BITS 0x00000007
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_RESET 0x00000000
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_RSTSEQ_DONE_CSI
|
||||
// Description : Indicates the current state of the reset
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_CSI_RESET 0x0
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_CSI_BITS 0x00000004
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_CSI_MSB 2
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_CSI_LSB 2
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_CSI_ACCESS "RO"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_RSTSEQ_DONE_DPI
|
||||
// Description : Indicates the current state of the reset
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_DPI_RESET 0x0
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_DPI_BITS 0x00000002
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_DPI_MSB 1
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_DPI_LSB 1
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_DPI_ACCESS "RO"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_RSTSEQ_DONE_BUSADAPTER
|
||||
// Description : Indicates the current state of the reset
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_BUSADAPTER_RESET 0x0
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_BUSADAPTER_BITS 0x00000001
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_BUSADAPTER_MSB 0
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_BUSADAPTER_LSB 0
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_BUSADAPTER_ACCESS "RO"
|
||||
// ================================================================================
|
||||
// Register : RPI_MIPICFG_DFTSS
|
||||
// JTAG access : asynchronous
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DFTSS_OFFSET 0x00000054
|
||||
#define RPI_MIPICFG_DFTSS_BITS 0x0000001f
|
||||
#define RPI_MIPICFG_DFTSS_RESET 0x00000000
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DFTSS_JTAG_COPY
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DFTSS_JTAG_COPY_RESET 0x0
|
||||
#define RPI_MIPICFG_DFTSS_JTAG_COPY_BITS 0x00000010
|
||||
#define RPI_MIPICFG_DFTSS_JTAG_COPY_MSB 4
|
||||
#define RPI_MIPICFG_DFTSS_JTAG_COPY_LSB 4
|
||||
#define RPI_MIPICFG_DFTSS_JTAG_COPY_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DFTSS_JTAG_ACCESS_ONLY
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DFTSS_JTAG_ACCESS_ONLY_RESET 0x0
|
||||
#define RPI_MIPICFG_DFTSS_JTAG_ACCESS_ONLY_BITS 0x00000008
|
||||
#define RPI_MIPICFG_DFTSS_JTAG_ACCESS_ONLY_MSB 3
|
||||
#define RPI_MIPICFG_DFTSS_JTAG_ACCESS_ONLY_LSB 3
|
||||
#define RPI_MIPICFG_DFTSS_JTAG_ACCESS_ONLY_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DFTSS_BYPASS_OUTSYNCS
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DFTSS_BYPASS_OUTSYNCS_RESET 0x0
|
||||
#define RPI_MIPICFG_DFTSS_BYPASS_OUTSYNCS_BITS 0x00000004
|
||||
#define RPI_MIPICFG_DFTSS_BYPASS_OUTSYNCS_MSB 2
|
||||
#define RPI_MIPICFG_DFTSS_BYPASS_OUTSYNCS_LSB 2
|
||||
#define RPI_MIPICFG_DFTSS_BYPASS_OUTSYNCS_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DFTSS_BYPASS_INSYNCS
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DFTSS_BYPASS_INSYNCS_RESET 0x0
|
||||
#define RPI_MIPICFG_DFTSS_BYPASS_INSYNCS_BITS 0x00000002
|
||||
#define RPI_MIPICFG_DFTSS_BYPASS_INSYNCS_MSB 1
|
||||
#define RPI_MIPICFG_DFTSS_BYPASS_INSYNCS_LSB 1
|
||||
#define RPI_MIPICFG_DFTSS_BYPASS_INSYNCS_ACCESS "RW"
|
||||
// --------------------------------------------------------------------------------
|
||||
// Field : RPI_MIPICFG_DFTSS_BYPASS_RESETSYNCS
|
||||
// Description : None
|
||||
#define RPI_MIPICFG_DFTSS_BYPASS_RESETSYNCS_RESET 0x0
|
||||
#define RPI_MIPICFG_DFTSS_BYPASS_RESETSYNCS_BITS 0x00000001
|
||||
#define RPI_MIPICFG_DFTSS_BYPASS_RESETSYNCS_MSB 0
|
||||
#define RPI_MIPICFG_DFTSS_BYPASS_RESETSYNCS_LSB 0
|
||||
#define RPI_MIPICFG_DFTSS_BYPASS_RESETSYNCS_ACCESS "RW"
|
||||
#define RPI_MIPICFG_CLK2FC_OFFSET 0x00000000
|
||||
#define RPI_MIPICFG_CFG_OFFSET 0x00000004
|
||||
#define RPI_MIPICFG_TE_OFFSET 0x00000008
|
||||
#define RPI_MIPICFG_DPHY_MONITOR_OFFSET 0x00000010
|
||||
#define RPI_MIPICFG_DPHY_CTRL_0_OFFSET 0x00000014
|
||||
#define RPI_MIPICFG_DPHY_CTRL_1_OFFSET 0x00000018
|
||||
#define RPI_MIPICFG_DPHY_CTRL_2_OFFSET 0x0000001c
|
||||
#define RPI_MIPICFG_DPHY_CTRL_3_OFFSET 0x00000020
|
||||
#define RPI_MIPICFG_DPHY_CTRL_4_OFFSET 0x00000024
|
||||
#define RPI_MIPICFG_INTR_OFFSET 0x00000028
|
||||
#define RPI_MIPICFG_INTE_OFFSET 0x0000002c
|
||||
#define RPI_MIPICFG_INTE_DSI_DMA_BITS 0x00000002
|
||||
#define RPI_MIPICFG_INTF_OFFSET 0x00000030
|
||||
#define RPI_MIPICFG_INTS_OFFSET 0x00000034
|
||||
#define RPI_MIPICFG_BLOCK_ID_OFFSET 0x00000038
|
||||
#define RPI_MIPICFG_INSTANCE_ID_OFFSET 0x0000003c
|
||||
#define RPI_MIPICFG_RSTSEQ_AUTO_OFFSET 0x00000040
|
||||
#define RPI_MIPICFG_RSTSEQ_PARALLEL_OFFSET 0x00000044
|
||||
#define RPI_MIPICFG_RSTSEQ_CTRL_OFFSET 0x00000048
|
||||
#define RPI_MIPICFG_RSTSEQ_TRIG_OFFSET 0x0000004c
|
||||
#define RPI_MIPICFG_RSTSEQ_DONE_OFFSET 0x00000050
|
||||
#define RPI_MIPICFG_DFTSS_OFFSET 0x00000054
|
||||
|
||||
#define CFG_WRITE(reg, val) writel((val), dsi->hw_base[RP1DSI_HW_BLOCK_CFG] + (reg ## _OFFSET))
|
||||
#define CFG_READ(reg) readl(dsi->hw_base[RP1DSI_HW_BLOCK_CFG] + (reg ## _OFFSET))
|
||||
#define CFG_WRITE(reg, val) writel((val), dsi->hw_base[RP1DSI_HW_BLOCK_CFG] + (reg ## _OFFSET))
|
||||
#define CFG_READ(reg) readl(dsi->hw_base[RP1DSI_HW_BLOCK_CFG] + (reg ## _OFFSET))
|
||||
|
||||
/* ------------------------------- DPHY setup stuff ------------------------ */
|
||||
|
||||
|
||||
Reference in New Issue
Block a user