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mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s28hx SEMPER flash

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Infineon(Cypress) SEMPER NOR flash family has on-die ECC and its program
granularity is 16-byte ECC data unit size. JFFS2 supports write buffer
mode for ECC'd NOR flash. Provide a way to clear the MTD_BIT_WRITEABLE
flag in order to enable JFFS2 write buffer mode support.

A new SNOR_F_ECC flag is introduced to determine if the part has on-die
ECC and if it has, MTD_BIT_WRITEABLE is unset.

In vendor specific driver, a common cypress_nor_ecc_init() helper is
added. This helper takes care for ECC related initialization for SEMPER
flash family by setting up params->writesize and SNOR_F_ECC.

Fixes: c3266af101 ("mtd: spi-nor: spansion: add support for Cypress Semper flash")
Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/d586723f6f12aaff44fbcd7b51e674b47ed554ed.1680760742.git.Takahiro.Kuwano@infineon.com
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
This commit is contained in:
Takahiro Kuwano
2023-04-06 15:17:44 +09:00
committed by Tudor Ambarus
parent c87c9b11c5
commit 9fd0945fe6
4 changed files with 17 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/mtd/spi-nor/core.c
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@@ -3407,6 +3407,9 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor)
mtd->name = dev_name(dev); mtd->name = dev_name(dev);
mtd->type = MTD_NORFLASH; mtd->type = MTD_NORFLASH;
mtd->flags = MTD_CAP_NORFLASH; mtd->flags = MTD_CAP_NORFLASH;
/* Unset BIT_WRITEABLE to enable JFFS2 write buffer for ECC'd NOR */
if (nor->flags & SNOR_F_ECC)
mtd->flags &= ~MTD_BIT_WRITEABLE;
if (nor->info->flags & SPI_NOR_NO_ERASE) if (nor->info->flags & SPI_NOR_NO_ERASE)
mtd->flags |= MTD_NO_ERASE; mtd->flags |= MTD_NO_ERASE;
else else

1
drivers/mtd/spi-nor/core.h
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@@ -131,6 +131,7 @@ enum spi_nor_option_flags {
SNOR_F_SOFT_RESET = BIT(12), SNOR_F_SOFT_RESET = BIT(12),
SNOR_F_SWP_IS_VOLATILE = BIT(13), SNOR_F_SWP_IS_VOLATILE = BIT(13),
SNOR_F_RWW = BIT(14), SNOR_F_RWW = BIT(14),
SNOR_F_ECC = BIT(15),
}; };
struct spi_nor_read_command { struct spi_nor_read_command {

1
drivers/mtd/spi-nor/debugfs.c
View File

@@ -26,6 +26,7 @@ static const char *const snor_f_names[] = {
SNOR_F_NAME(SOFT_RESET), SNOR_F_NAME(SOFT_RESET),
SNOR_F_NAME(SWP_IS_VOLATILE), SNOR_F_NAME(SWP_IS_VOLATILE),
SNOR_F_NAME(RWW), SNOR_F_NAME(RWW),
SNOR_F_NAME(ECC),
}; };
#undef SNOR_F_NAME #undef SNOR_F_NAME

13
drivers/mtd/spi-nor/spansion.c
View File

@@ -332,6 +332,17 @@ static int cypress_nor_set_page_size(struct spi_nor *nor)
return 0; return 0;
} }
static void cypress_nor_ecc_init(struct spi_nor *nor)
{
/*
* Programming is supported only in 16-byte ECC data unit granularity.
* Byte-programming, bit-walking, or multiple program operations to the
* same ECC data unit without an erase are not allowed.
*/
nor->params->writesize = 16;
nor->flags |= SNOR_F_ECC;
}
static int static int
s25fs256t_post_bfpt_fixup(struct spi_nor *nor, s25fs256t_post_bfpt_fixup(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header, const struct sfdp_parameter_header *bfpt_header,
@@ -506,7 +517,7 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor,
static void s28hx_t_late_init(struct spi_nor *nor) static void s28hx_t_late_init(struct spi_nor *nor)
{ {
nor->params->octal_dtr_enable = cypress_nor_octal_dtr_enable; nor->params->octal_dtr_enable = cypress_nor_octal_dtr_enable;
nor->params->writesize = 16; cypress_nor_ecc_init(nor);
} }
static const struct spi_nor_fixups s28hx_t_fixups = { static const struct spi_nor_fixups s28hx_t_fixups = {