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spi: lpspi: Fix CLK pin becomes low before one transfer

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Remove Reset operation in fsl_lpspi_config(). This RST may cause both CLK
and CS pins go from high to low level under cs-gpio mode.
Add fsl_lpspi_reset() function after one message transfer to clear all
flags in use.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Clark Wang
2019-01-07 07:47:43 +00:00
committed by Mark Brown
parent 6a13044849
commit a15dc3d657
1 changed files with 20 additions and 4 deletions
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24
drivers/spi/spi-fsl-lpspi.c
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@@ -268,10 +268,6 @@ static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
u32 temp; u32 temp;
int ret; int ret;
temp = CR_RST;
writel(temp, fsl_lpspi->base + IMX7ULP_CR);
writel(0, fsl_lpspi->base + IMX7ULP_CR);
if (!fsl_lpspi->is_slave) { if (!fsl_lpspi->is_slave) {
ret = fsl_lpspi_set_bitrate(fsl_lpspi); ret = fsl_lpspi_set_bitrate(fsl_lpspi);
if (ret) if (ret)
@@ -362,6 +358,24 @@ static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
return 0; return 0;
} }
static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
{
u32 temp;
/* Disable all interrupt */
fsl_lpspi_intctrl(fsl_lpspi, 0);
/* W1C for all flags in SR */
temp = 0x3F << 8;
writel(temp, fsl_lpspi->base + IMX7ULP_SR);
/* Clear FIFO and disable module */
temp = CR_RRF | CR_RTF;
writel(temp, fsl_lpspi->base + IMX7ULP_CR);
return 0;
}
static int fsl_lpspi_transfer_one(struct spi_controller *controller, static int fsl_lpspi_transfer_one(struct spi_controller *controller,
struct spi_device *spi, struct spi_device *spi,
struct spi_transfer *t) struct spi_transfer *t)
@@ -383,6 +397,8 @@ static int fsl_lpspi_transfer_one(struct spi_controller *controller,
if (ret) if (ret)
return ret; return ret;
fsl_lpspi_reset(fsl_lpspi);
return 0; return 0;
} }