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octeontx2-af: cn10k: Use FLIT0 register instead of FLIT1

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[ Upstream commit 623da5ca70 ]

RVU SMMU widget stores the final translated PA at
RVU_AF_SMMU_TLN_FLIT0<57:18> instead of FLIT1 register. This patch
fixes the address translation logic to use the correct register.

Fixes: 893ae97214 ("octeontx2-af: cn10k: Support configurable LMTST regions")
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Geetha sowjanya
2021-08-22 17:32:27 +05:30
committed by Greg Kroah-Hartman
parent 392faa331b
commit a181e99b0b
2 changed files with 3 additions and 3 deletions
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4
drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
View File

@@ -82,10 +82,10 @@ static int rvu_get_lmtaddr(struct rvu *rvu, u16 pcifunc,
dev_err(rvu->dev, "%s LMTLINE iova transulation failed err:%llx\n", __func__, val); dev_err(rvu->dev, "%s LMTLINE iova transulation failed err:%llx\n", __func__, val);
return -EIO; return -EIO;
} }
/* PA[51:12] = RVU_AF_SMMU_TLN_FLIT1[60:21] /* PA[51:12] = RVU_AF_SMMU_TLN_FLIT0[57:18]
* PA[11:0] = IOVA[11:0] * PA[11:0] = IOVA[11:0]
*/ */
pa = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TLN_FLIT1) >> 21; pa = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TLN_FLIT0) >> 18;
pa &= GENMASK_ULL(39, 0); pa &= GENMASK_ULL(39, 0);
*lmt_addr = (pa << 12) | (iova & 0xFFF); *lmt_addr = (pa << 12) | (iova & 0xFFF);

2
drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
View File

@@ -53,7 +53,7 @@
#define RVU_AF_SMMU_TXN_REQ (0x6008) #define RVU_AF_SMMU_TXN_REQ (0x6008)
#define RVU_AF_SMMU_ADDR_RSP_STS (0x6010) #define RVU_AF_SMMU_ADDR_RSP_STS (0x6010)
#define RVU_AF_SMMU_ADDR_TLN (0x6018) #define RVU_AF_SMMU_ADDR_TLN (0x6018)
#define RVU_AF_SMMU_TLN_FLIT1 (0x6030) #define RVU_AF_SMMU_TLN_FLIT0 (0x6020)
/* Admin function's privileged PF/VF registers */ /* Admin function's privileged PF/VF registers */
#define RVU_PRIV_CONST (0x8000000) #define RVU_PRIV_CONST (0x8000000)