From a8677922e28cbb8193e7fae571e6551a20358d0b Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Wed, 12 Nov 2025 14:12:57 +0000 Subject: [PATCH] mmc: bcm2835: Relax the 50MHz overclock check EMMC clock speeds are based around divisions of 52Mhz, not the 50MHz used by SD. As such, relax the "full speed" check (intended to stop any overclock whenever an operation has to be retried) so that any requested speed of 50MHz or higher will be overclocked. Signed-off-by: Phil Elwell --- drivers/mmc/host/bcm2835.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/bcm2835.c b/drivers/mmc/host/bcm2835.c index 63ab693f1f66..2278caee3650 100644 --- a/drivers/mmc/host/bcm2835.c +++ b/drivers/mmc/host/bcm2835.c @@ -1128,7 +1128,7 @@ static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock) const unsigned int MHZ = 1000000; int div; - if (host->overclock_50 && (clock == 50*MHZ)) + if (host->overclock_50 && (clock >= 50*MHZ)) clock = host->overclock_50 * MHZ + (MHZ - 1); /* The SDCDIV register has 11 bits, and holds (div - 2). But