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drm/vc4: crtc: Add BCM2711 pixelvalves

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The BCM2711 has 5 pixelvalves, so now that our driver is ready, let's add
support for them.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
This commit is contained in:
Maxime Ripard
2019-12-26 11:35:58 +01:00
committed by popcornmix
parent 26613c79b7
commit aa43601d97
2 changed files with 86 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

82
drivers/gpu/drm/vc4/vc4_crtc.c
View File

@@ -273,6 +273,13 @@ static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
case PV_CONTROL_FORMAT_24:
case PV_CONTROL_FORMAT_DSIV_24:
default:
/*
* For some reason, the pixelvalve4 doesn't work with
* the usual formula and will only work with 32.
*/
if (vc4_crtc->data->hvs_output == 5)
return 32;
return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
}
}
@@ -281,8 +288,14 @@ static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc,
u32 format)
{
u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
return VC4_SET_FIELD(level & 0x3f,
PV_CONTROL_FIFO_LEVEL);
u32 ret = 0;
if (level > 0x3f)
ret |= VC4_SET_FIELD((level >> 6) & 0x3,
PV5_CONTROL_FIFO_LEVEL_HIGH);
return ret | VC4_SET_FIELD(level & 0x3f,
PV_CONTROL_FIFO_LEVEL);
}
/*
@@ -328,6 +341,9 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
CRTC_WRITE(PV_CONTROL, 0);
CRTC_WRITE(PV_MUX_CFG,
VC4_SET_FIELD(8, PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
CRTC_WRITE(PV_HORZA,
VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
PV_HORZA_HBP) |
@@ -1115,10 +1131,72 @@ static const struct vc4_crtc_data bcm2835_pv2_data = {
},
};
static const struct vc4_crtc_data bcm2711_pv0_data = {
.debugfs_name = "crtc0_regs",
.hvs_available_channels = BIT(0),
.hvs_output = 0,
.fifo_depth = 64,
.pixels_per_clock = 1,
.encoder_types = {
[0] = VC4_ENCODER_TYPE_DSI0,
[1] = VC4_ENCODER_TYPE_DPI,
},
};
static const struct vc4_crtc_data bcm2711_pv1_data = {
.debugfs_name = "crtc1_regs",
.hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
.hvs_output = 3,
.fifo_depth = 64,
.pixels_per_clock = 1,
.encoder_types = {
[0] = VC4_ENCODER_TYPE_DSI1,
[1] = VC4_ENCODER_TYPE_SMI,
},
};
static const struct vc4_crtc_data bcm2711_pv2_data = {
.debugfs_name = "crtc2_regs",
.hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
.hvs_output = 4,
.fifo_depth = 256,
.pixels_per_clock = 2,
.encoder_types = {
[0] = VC4_ENCODER_TYPE_HDMI0,
},
};
static const struct vc4_crtc_data bcm2711_pv3_data = {
.debugfs_name = "crtc3_regs",
.hvs_available_channels = BIT(1),
.hvs_output = 1,
.fifo_depth = 64,
.pixels_per_clock = 1,
.encoder_types = {
[0] = VC4_ENCODER_TYPE_VEC,
},
};
static const struct vc4_crtc_data bcm2711_pv4_data = {
.debugfs_name = "crtc4_regs",
.hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
.hvs_output = 5,
.fifo_depth = 64,
.pixels_per_clock = 2,
.encoder_types = {
[0] = VC4_ENCODER_TYPE_HDMI1,
},
};
static const struct of_device_id vc4_crtc_dt_match[] = {
{ .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
{ .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
{ .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
{ .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
{ .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
{ .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
{ .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
{ .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
{}
};

6
drivers/gpu/drm/vc4/vc4_regs.h
View File

@@ -130,6 +130,8 @@
#define V3D_ERRSTAT 0x00f20
#define PV_CONTROL 0x00
# define PV5_CONTROL_FIFO_LEVEL_HIGH_MASK VC4_MASK(26, 25)
# define PV5_CONTROL_FIFO_LEVEL_HIGH_SHIFT 25
# define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21)
# define PV_CONTROL_FORMAT_SHIFT 21
# define PV_CONTROL_FORMAT_24 0
@@ -209,6 +211,10 @@
#define PV_HACT_ACT 0x30
#define PV_MUX_CFG 0x34
# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_MASK VC4_MASK(5, 2)
# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_SHIFT 2
#define SCALER_CHANNELS_COUNT 3
#define SCALER_DISPCTRL 0x00000000