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drm/vc4: Ensure DSI is enabled for FIFO resets

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The block must be enabled for the FIFO resets to be actioned,
so ensure this is the case.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
This commit is contained in:
Dave Stevenson
2024-04-05 17:51:55 +01:00
committed by Dom Cobley
parent 7d166cfd30
commit b063ae8c8d
1 changed files with 8 additions and 8 deletions
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16
drivers/gpu/drm/vc4/vc4_dsi.c
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@@ -411,7 +411,8 @@
# define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1)
# define DSI0_CTRL_CTRL0 BIT(0)
# define DSI1_CTRL_EN BIT(0)
# define DSI0_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
# define DSI0_CTRL_RESET_FIFOS (DSI0_CTRL_CTRL0 | \
DSI_CTRL_CLR_LDF | \
DSI0_CTRL_CLR_PBCF | \
DSI0_CTRL_CLR_CPBCF | \
DSI0_CTRL_CLR_PDF | \
@@ -963,12 +964,17 @@ static void vc4_dsi_bridge_pre_enable(struct drm_bridge *bridge,
hs_clock = clk_get_rate(dsi->pll_phy_clock);
/* Reset the DSI and all its fifos. */
/*
* Reset the DSI and all its fifos. The block must be enabled for the
* FIFO resets to trigger.
*/
DSI_PORT_WRITE(CTRL,
DSI_CTRL_SOFT_RESET_CFG |
DSI_PORT_BIT(CTRL_RESET_FIFOS));
DSI_PORT_WRITE(CTRL,
((dsi->variant->port == 0) ?
DSI0_CTRL_CTRL0 : DSI1_CTRL_EN) |
DSI_CTRL_HSDT_EOT_DISABLE |
DSI_CTRL_RX_LPDT_EOT_DISABLE);
@@ -1142,12 +1148,6 @@ static void vc4_dsi_bridge_pre_enable(struct drm_bridge *bridge,
DSI_DISP1_PFORMAT) |
DSI_DISP1_ENABLE);
/* Ungate the block. */
if (dsi->variant->port == 0)
DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0);
else
DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);
/* Bring AFE out of reset. */
DSI_PORT_WRITE(PHY_AFEC0,
DSI_PORT_READ(PHY_AFEC0) &