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drm/vc4: plane: Add support for 2712 D-step.

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There are a few minor changes in the display list generation
for the D-step of the chip, so add them.

Reviewed-by: Maxime Ripard <mripard@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20241025-drm-vc4-2712-support-v2-24-35efa83c8fc0@raspberrypi.com
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
This commit is contained in:
Dave Stevenson
2024-10-25 18:15:55 +01:00
parent b460e0072c
commit b7b14b31c8
2 changed files with 60 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
drivers/gpu/drm/vc4/vc4_plane.c
View File

@@ -1134,6 +1134,13 @@ static u32 vc4_hvs4_get_alpha_blend_mode(struct drm_plane_state *state)
static u32 vc4_hvs5_get_alpha_blend_mode(struct drm_plane_state *state) static u32 vc4_hvs5_get_alpha_blend_mode(struct drm_plane_state *state)
{ {
struct drm_device *dev = state->state->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
switch (vc4->gen) {
default:
case VC4_GEN_5:
case VC4_GEN_6_C:
if (!state->fb->format->has_alpha) if (!state->fb->format->has_alpha)
return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_FIXED, return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_FIXED,
SCALER5_CTL2_ALPHA_MODE); SCALER5_CTL2_ALPHA_MODE);
@@ -1151,6 +1158,27 @@ static u32 vc4_hvs5_get_alpha_blend_mode(struct drm_plane_state *state)
return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_PIPELINE, return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_PIPELINE,
SCALER5_CTL2_ALPHA_MODE); SCALER5_CTL2_ALPHA_MODE);
} }
case VC4_GEN_6_D:
/* 2712-D configures fixed alpha mode in CTL0 */
return state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI ?
SCALER5_CTL2_ALPHA_PREMULT : 0;
}
}
static u32 vc4_hvs6_get_alpha_mask_mode(struct drm_plane_state *state)
{
struct drm_device *dev = state->state->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
WARN_ON_ONCE(vc4->gen != VC4_GEN_6_C && vc4->gen != VC4_GEN_6_D);
if (vc4->gen == VC4_GEN_6_D &&
(!state->fb->format->has_alpha ||
state->pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE))
return VC4_SET_FIELD(SCALER6D_CTL0_ALPHA_MASK_FIXED,
SCALER6_CTL0_ALPHA_MASK);
return VC4_SET_FIELD(SCALER6_CTL0_ALPHA_MASK_NONE, SCALER6_CTL0_ALPHA_MASK);
} }
/* Writes out a full display list for an active plane to the plane's /* Writes out a full display list for an active plane to the plane's
@@ -1645,14 +1673,13 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
static u32 vc6_plane_get_csc_mode(struct vc4_plane_state *vc4_state) static u32 vc6_plane_get_csc_mode(struct vc4_plane_state *vc4_state)
{ {
struct drm_plane_state *state = &vc4_state->base; struct drm_plane_state *state = &vc4_state->base;
struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev);
u32 ret = 0; u32 ret = 0;
if (vc4_state->is_yuv) { if (vc4_state->is_yuv) {
enum drm_color_encoding color_encoding = state->color_encoding; enum drm_color_encoding color_encoding = state->color_encoding;
enum drm_color_range color_range = state->color_range; enum drm_color_range color_range = state->color_range;
ret |= SCALER6_CTL2_CSC_ENABLE;
/* CSC pre-loaded with: /* CSC pre-loaded with:
* 0 = BT601 limited range * 0 = BT601 limited range
* 1 = BT709 limited range * 1 = BT709 limited range
@@ -1666,8 +1693,15 @@ static u32 vc6_plane_get_csc_mode(struct vc4_plane_state *vc4_state)
if (color_range > DRM_COLOR_YCBCR_FULL_RANGE) if (color_range > DRM_COLOR_YCBCR_FULL_RANGE)
color_range = DRM_COLOR_YCBCR_LIMITED_RANGE; color_range = DRM_COLOR_YCBCR_LIMITED_RANGE;
if (vc4->gen == VC4_GEN_6_C) {
ret |= SCALER6C_CTL2_CSC_ENABLE;
ret |= VC4_SET_FIELD(color_encoding + (color_range * 3), ret |= VC4_SET_FIELD(color_encoding + (color_range * 3),
SCALER6_CTL2_BRCM_CFC_CONTROL); SCALER6C_CTL2_BRCM_CFC_CONTROL);
} else {
ret |= SCALER6D_CTL2_CSC_ENABLE;
ret |= VC4_SET_FIELD(color_encoding + (color_range * 3),
SCALER6D_CTL2_BRCM_CFC_CONTROL);
}
} }
return ret; return ret;
@@ -1880,7 +1914,7 @@ static int vc6_plane_mode_set(struct drm_plane *plane,
vc4_dlist_write(vc4_state, vc4_dlist_write(vc4_state,
SCALER6_CTL0_VALID | SCALER6_CTL0_VALID |
VC4_SET_FIELD(tiling, SCALER6_CTL0_ADDR_MODE) | VC4_SET_FIELD(tiling, SCALER6_CTL0_ADDR_MODE) |
VC4_SET_FIELD(0, SCALER6_CTL0_ALPHA_MASK) | vc4_hvs6_get_alpha_mask_mode(state) |
(vc4_state->is_unity ? SCALER6_CTL0_UNITY : 0) | (vc4_state->is_unity ? SCALER6_CTL0_UNITY : 0) |
VC4_SET_FIELD(format->pixel_order_hvs5, SCALER6_CTL0_ORDERRGBA) | VC4_SET_FIELD(format->pixel_order_hvs5, SCALER6_CTL0_ORDERRGBA) |
VC4_SET_FIELD(scl1, SCALER6_CTL0_SCL1_MODE) | VC4_SET_FIELD(scl1, SCALER6_CTL0_SCL1_MODE) |

9
drivers/gpu/drm/vc4/vc4_regs.h
View File

@@ -1194,6 +1194,9 @@ enum hvs_pixel_format {
#define SCALER5_CTL2_ALPHA_MASK VC4_MASK(15, 4) #define SCALER5_CTL2_ALPHA_MASK VC4_MASK(15, 4)
#define SCALER5_CTL2_ALPHA_SHIFT 4 #define SCALER5_CTL2_ALPHA_SHIFT 4
#define SCALER6D_CTL2_CSC_ENABLE BIT(19)
#define SCALER6D_CTL2_BRCM_CFC_CONTROL_MASK VC4_MASK(22, 20)
#define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16) #define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
#define SCALER_POS1_SCL_HEIGHT_SHIFT 16 #define SCALER_POS1_SCL_HEIGHT_SHIFT 16
@@ -1347,6 +1350,8 @@ enum hvs_pixel_format {
#define SCALER6_CTL0_ADDR_MODE_UIF 4 #define SCALER6_CTL0_ADDR_MODE_UIF 4
#define SCALER6_CTL0_ALPHA_MASK_MASK VC4_MASK(19, 18) #define SCALER6_CTL0_ALPHA_MASK_MASK VC4_MASK(19, 18)
#define SCALER6_CTL0_ALPHA_MASK_NONE 0
#define SCALER6D_CTL0_ALPHA_MASK_FIXED 3
#define SCALER6_CTL0_UNITY BIT(15) #define SCALER6_CTL0_UNITY BIT(15)
#define SCALER6_CTL0_ORDERRGBA_MASK VC4_MASK(14, 13) #define SCALER6_CTL0_ORDERRGBA_MASK VC4_MASK(14, 13)
#define SCALER6_CTL0_SCL1_MODE_MASK VC4_MASK(10, 8) #define SCALER6_CTL0_SCL1_MODE_MASK VC4_MASK(10, 8)
@@ -1361,8 +1366,8 @@ enum hvs_pixel_format {
#define SCALER6_CTL2_ALPHA_PREMULT BIT(29) #define SCALER6_CTL2_ALPHA_PREMULT BIT(29)
#define SCALER6_CTL2_ALPHA_MIX BIT(28) #define SCALER6_CTL2_ALPHA_MIX BIT(28)
#define SCALER6_CTL2_BFG BIT(26) #define SCALER6_CTL2_BFG BIT(26)
#define SCALER6_CTL2_CSC_ENABLE BIT(25) #define SCALER6C_CTL2_CSC_ENABLE BIT(25)
#define SCALER6_CTL2_BRCM_CFC_CONTROL_MASK VC4_MASK(18, 16) #define SCALER6C_CTL2_BRCM_CFC_CONTROL_MASK VC4_MASK(18, 16)
#define SCALER6_CTL2_ALPHA_MASK VC4_MASK(15, 4) #define SCALER6_CTL2_ALPHA_MASK VC4_MASK(15, 4)
#define SCALER6_POS1_SCL_LINES_MASK VC4_MASK(28, 16) #define SCALER6_POS1_SCL_LINES_MASK VC4_MASK(28, 16)