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drm/vc4: Correct HDMI timing registers for interlaced modes

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For interlaced modes the timings were not being correctly
programmed into the HDMI block, so correct them.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
This commit is contained in:
Dave Stevenson
2022-05-17 17:32:04 +01:00
committed by Phil Elwell
parent 5efa79bc79
commit c0ba150ce4
1 changed files with 4 additions and 4 deletions
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8
drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -1241,13 +1241,13 @@ static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
VC5_HDMI_VERTA_VFP) | VC5_HDMI_VERTA_VFP) |
VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + VC5_HDMI_VERTB_VSPO) |
interlaced, VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
VC4_HDMI_VERTB_VBP)); VC4_HDMI_VERTB_VBP));
u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
VC4_SET_FIELD(mode->crtc_vtotal - VC4_SET_FIELD(mode->crtc_vtotal -
mode->crtc_vsync_end, mode->crtc_vsync_end - interlaced,
VC4_HDMI_VERTB_VBP)); VC4_HDMI_VERTB_VBP));
unsigned long flags; unsigned long flags;
unsigned char gcp; unsigned char gcp;