mirror of
https://github.com/raspberrypi/linux.git
synced 2025-12-06 10:00:17 +00:00
mfd: Add rp1 driver
RP1 is a multifunction PCIe device that exposes a range of peripherals. Add the parent driver to manage these. Signed-off-by: Phil Elwell <phil@raspberrypi.com>
This commit is contained in:
Phil Elwell
Dom Cobley
@@ -2324,6 +2324,17 @@ config MFD_INTEL_M10_BMC_PMCI
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additional drivers must be enabled in order to use the functionality
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of the device.
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config MFD_RP1
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tristate "RP1 MFD driver"
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depends on PCI
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select MFD_CORE
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help
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Support for the RP1 peripheral chip.
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This driver provides support for the Raspberry Pi RP1 peripheral chip.
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It is responsible for enabling the Device Tree node once the PCIe endpoint
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has been configured, and handling interrupts.
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config MFD_RSMU_I2C
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tristate "Renesas Synchronization Management Unit with I2C"
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depends on I2C && OF
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@@ -285,3 +285,5 @@ rsmu-i2c-objs := rsmu_core.o rsmu_i2c.o
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rsmu-spi-objs := rsmu_core.o rsmu_spi.o
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obj-$(CONFIG_MFD_RSMU_I2C) += rsmu-i2c.o
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obj-$(CONFIG_MFD_RSMU_SPI) += rsmu-spi.o
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obj-$(CONFIG_MFD_RP1) += rp1.o
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367
drivers/mfd/rp1.c
Normal file
367
drivers/mfd/rp1.c
Normal file
@@ -0,0 +1,367 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018-22 Raspberry Pi Ltd.
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* All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/completion.h>
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#include <linux/etherdevice.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/mfd/core.h>
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#include <linux/mmc/host.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/of_platform.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/rp1_platform.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <dt-bindings/mfd/rp1.h>
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/* TO DO:
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* 1. Occasional shutdown crash - RP1 being closed before its children?
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* 2. DT mode interrupt handling.
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*/
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#define RP1_DRIVER_NAME "rp1"
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#define PCI_VENDOR_ID_RPI 0x1de4
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#define PCI_DEVICE_ID_RP1_C0 0x0001
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#define PCI_DEVICE_REV_RP1_C0 2
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#define RP1_ACTUAL_IRQS RP1_INT_END
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#define RP1_IRQS RP1_ACTUAL_IRQS
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#define RP1_SYSCLK_RATE 200000000
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#define RP1_SYSCLK_FPGA_RATE 60000000
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// Don't want to include the whole sysinfo reg header
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#define SYSINFO_CHIP_ID_OFFSET 0x00000000
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#define SYSINFO_PLATFORM_OFFSET 0x00000004
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#define REG_RW 0x000
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#define REG_SET 0x800
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#define REG_CLR 0xc00
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// MSIX CFG registers start at 0x8
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#define MSIX_CFG(x) (0x8 + (4 * (x)))
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#define MSIX_CFG_IACK_EN BIT(3)
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#define MSIX_CFG_IACK BIT(2)
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#define MSIX_CFG_TEST BIT(1)
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#define MSIX_CFG_ENABLE BIT(0)
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#define INTSTATL 0x108
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#define INTSTATH 0x10c
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struct rp1_dev {
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struct pci_dev *pdev;
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struct device *dev;
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resource_size_t bar_start;
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resource_size_t bar_end;
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struct clk *sys_clk;
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struct irq_domain *domain;
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struct irq_data *pcie_irqds[64];
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void __iomem *msix_cfg_regs;
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};
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static bool rp1_level_triggered_irq[RP1_ACTUAL_IRQS] = { 0 };
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static struct rp1_dev *g_rp1;
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static u32 g_chip_id, g_platform;
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static void dump_bar(struct pci_dev *pdev, unsigned int bar)
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{
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dev_info(&pdev->dev,
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"bar%d len 0x%llx, start 0x%llx, end 0x%llx, flags, 0x%lx\n",
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bar,
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pci_resource_len(pdev, bar),
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pci_resource_start(pdev, bar),
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pci_resource_end(pdev, bar),
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pci_resource_flags(pdev, bar));
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}
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static void msix_cfg_set(struct rp1_dev *rp1, unsigned int hwirq, u32 value)
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{
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writel(value, rp1->msix_cfg_regs + REG_SET + MSIX_CFG(hwirq));
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}
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static void msix_cfg_clr(struct rp1_dev *rp1, unsigned int hwirq, u32 value)
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{
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writel(value, rp1->msix_cfg_regs + REG_CLR + MSIX_CFG(hwirq));
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}
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static void rp1_mask_irq(struct irq_data *irqd)
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{
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struct rp1_dev *rp1 = irqd->domain->host_data;
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struct irq_data *pcie_irqd = rp1->pcie_irqds[irqd->hwirq];
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pci_msi_mask_irq(pcie_irqd);
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}
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static void rp1_unmask_irq(struct irq_data *irqd)
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{
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struct rp1_dev *rp1 = irqd->domain->host_data;
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struct irq_data *pcie_irqd = rp1->pcie_irqds[irqd->hwirq];
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pci_msi_unmask_irq(pcie_irqd);
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}
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static int rp1_irq_set_type(struct irq_data *irqd, unsigned int type)
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{
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struct rp1_dev *rp1 = irqd->domain->host_data;
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unsigned int hwirq = (unsigned int)irqd->hwirq;
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int ret = 0;
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
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dev_dbg(rp1->dev, "MSIX IACK EN for irq %d\n", hwirq);
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msix_cfg_set(rp1, hwirq, MSIX_CFG_IACK_EN);
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rp1_level_triggered_irq[hwirq] = true;
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break;
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case IRQ_TYPE_EDGE_RISING:
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msix_cfg_clr(rp1, hwirq, MSIX_CFG_IACK_EN);
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rp1_level_triggered_irq[hwirq] = false;
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static struct irq_chip rp1_irq_chip = {
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.name = "rp1_irq_chip",
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.irq_mask = rp1_mask_irq,
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.irq_unmask = rp1_unmask_irq,
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.irq_set_type = rp1_irq_set_type,
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};
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static void rp1_chained_handle_irq(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct rp1_dev *rp1 = desc->irq_data.chip_data;
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unsigned int hwirq = desc->irq_data.hwirq & 0x3f;
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int new_irq;
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rp1 = g_rp1;
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chained_irq_enter(chip, desc);
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new_irq = irq_linear_revmap(rp1->domain, hwirq);
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generic_handle_irq(new_irq);
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if (rp1_level_triggered_irq[hwirq])
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msix_cfg_set(rp1, hwirq, MSIX_CFG_IACK);
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chained_irq_exit(chip, desc);
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}
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static int rp1_irq_xlate(struct irq_domain *d, struct device_node *node,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq, unsigned int *out_type)
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{
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struct rp1_dev *rp1 = d->host_data;
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struct irq_data *pcie_irqd;
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unsigned long hwirq;
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int pcie_irq;
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int ret;
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ret = irq_domain_xlate_twocell(d, node, intspec, intsize,
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&hwirq, out_type);
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if (!ret) {
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pcie_irq = pci_irq_vector(rp1->pdev, hwirq);
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pcie_irqd = irq_get_irq_data(pcie_irq);
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rp1->pcie_irqds[hwirq] = pcie_irqd;
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*out_hwirq = hwirq;
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}
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return ret;
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}
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static int rp1_irq_activate(struct irq_domain *d, struct irq_data *irqd,
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bool reserve)
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{
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struct rp1_dev *rp1 = d->host_data;
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struct irq_data *pcie_irqd;
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pcie_irqd = rp1->pcie_irqds[irqd->hwirq];
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msix_cfg_set(rp1, (unsigned int)irqd->hwirq, MSIX_CFG_ENABLE);
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return irq_domain_activate_irq(pcie_irqd, reserve);
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}
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static void rp1_irq_deactivate(struct irq_domain *d, struct irq_data *irqd)
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{
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struct rp1_dev *rp1 = d->host_data;
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struct irq_data *pcie_irqd;
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pcie_irqd = rp1->pcie_irqds[irqd->hwirq];
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msix_cfg_clr(rp1, (unsigned int)irqd->hwirq, MSIX_CFG_ENABLE);
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return irq_domain_deactivate_irq(pcie_irqd);
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}
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static const struct irq_domain_ops rp1_domain_ops = {
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.xlate = rp1_irq_xlate,
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.activate = rp1_irq_activate,
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.deactivate = rp1_irq_deactivate,
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};
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static inline dma_addr_t rp1_io_to_phys(struct rp1_dev *rp1, unsigned int offset)
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{
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return rp1->bar_start + offset;
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}
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static u32 rp1_reg_read(struct rp1_dev *rp1, unsigned int base_addr, u32 offset)
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{
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dma_addr_t phys = rp1_io_to_phys(rp1, base_addr);
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void __iomem *regblock = ioremap(phys, 0x1000);
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u32 value = readl(regblock + offset);
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iounmap(regblock);
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return value;
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}
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void rp1_get_platform(u32 *chip_id, u32 *platform)
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{
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if (chip_id)
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*chip_id = g_chip_id;
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if (platform)
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*platform = g_platform;
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}
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EXPORT_SYMBOL_GPL(rp1_get_platform);
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static int rp1_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct reset_control *reset;
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struct platform_device *pcie_pdev;
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struct device_node *rp1_node;
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struct rp1_dev *rp1;
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int err = 0;
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int i;
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reset = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
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if (IS_ERR(reset))
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return PTR_ERR(reset);
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reset_control_reset(reset);
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dump_bar(pdev, 0);
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dump_bar(pdev, 1);
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if (pci_resource_len(pdev, 1) <= 0x10000) {
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dev_err(&pdev->dev,
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"Not initialised - is the firmware running?\n");
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return -EINVAL;
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}
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/* enable pci device */
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err = pcim_enable_device(pdev);
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if (err < 0) {
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dev_err(&pdev->dev, "Enabling PCI device has failed: %d",
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err);
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return err;
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}
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pci_set_master(pdev);
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err = pci_alloc_irq_vectors(pdev, RP1_IRQS, RP1_IRQS,
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PCI_IRQ_MSIX);
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if (err != RP1_IRQS) {
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dev_err(&pdev->dev, "pci_alloc_irq_vectors failed - %d\n", err);
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return err;
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}
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rp1 = devm_kzalloc(&pdev->dev, sizeof(*rp1), GFP_KERNEL);
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if (!rp1)
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return -ENOMEM;
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rp1->pdev = pdev;
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rp1->dev = &pdev->dev;
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pci_set_drvdata(pdev, rp1);
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rp1->bar_start = pci_resource_start(pdev, 1);
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rp1->bar_end = pci_resource_end(pdev, 1);
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// Get chip id
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g_chip_id = rp1_reg_read(rp1, RP1_SYSINFO_BASE, SYSINFO_CHIP_ID_OFFSET);
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g_platform = rp1_reg_read(rp1, RP1_SYSINFO_BASE, SYSINFO_PLATFORM_OFFSET);
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dev_info(&pdev->dev, "chip_id 0x%x%s\n", g_chip_id,
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(g_platform & RP1_PLATFORM_FPGA) ? " FPGA" : "");
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if (g_chip_id != RP1_C0_CHIP_ID) {
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dev_err(&pdev->dev, "wrong chip id (%x)\n", g_chip_id);
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return -EINVAL;
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}
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rp1_node = of_find_node_by_name(NULL, "rp1");
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if (!rp1_node) {
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dev_err(&pdev->dev, "failed to find RP1 DT node\n");
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return -EINVAL;
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}
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pcie_pdev = of_find_device_by_node(rp1_node->parent);
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rp1->domain = irq_domain_add_linear(rp1_node, RP1_IRQS,
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&rp1_domain_ops, rp1);
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g_rp1 = rp1;
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/* TODO can this go in the rp1 device tree entry? */
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rp1->msix_cfg_regs = ioremap(rp1_io_to_phys(rp1, RP1_PCIE_APBS_BASE), 0x1000);
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for (i = 0; i < RP1_IRQS; i++) {
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int irq = irq_create_mapping(rp1->domain, i);
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if (irq < 0) {
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dev_err(&pdev->dev, "failed to create irq mapping\n");
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return irq;
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}
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irq_set_chip_data(irq, rp1);
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irq_set_chip_and_handler(irq, &rp1_irq_chip, handle_level_irq);
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irq_set_probe(irq);
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irq_set_chained_handler(pci_irq_vector(pdev, i),
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rp1_chained_handle_irq);
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}
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if (rp1_node)
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of_platform_populate(rp1_node, NULL, NULL, &pcie_pdev->dev);
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of_node_put(rp1_node);
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return 0;
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}
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static void rp1_remove(struct pci_dev *pdev)
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{
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struct rp1_dev *rp1 = pci_get_drvdata(pdev);
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mfd_remove_devices(&pdev->dev);
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clk_unregister(rp1->sys_clk);
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}
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static const struct pci_device_id dev_id_table[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_RPI, PCI_DEVICE_ID_RP1_C0), },
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{ 0, }
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};
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static struct pci_driver rp1_driver = {
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.name = RP1_DRIVER_NAME,
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.id_table = dev_id_table,
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.probe = rp1_probe,
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.remove = rp1_remove,
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};
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module_pci_driver(rp1_driver);
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MODULE_AUTHOR("Phil Elwell <phil@raspberrypi.com>");
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MODULE_DESCRIPTION("RP1 wrapper");
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MODULE_LICENSE("GPL");
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20
include/linux/rp1_platform.h
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20
include/linux/rp1_platform.h
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@@ -0,0 +1,20 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021-2022 Raspberry Pi Ltd.
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* All rights reserved.
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*/
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#ifndef _RP1_PLATFORM_H
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#define _RP1_PLATFORM_H
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#include <vdso/bits.h>
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#define RP1_B0_CHIP_ID 0x10001927
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#define RP1_C0_CHIP_ID 0x20001927
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#define RP1_PLATFORM_ASIC BIT(1)
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#define RP1_PLATFORM_FPGA BIT(0)
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void rp1_get_platform(u32 *chip_id, u32 *platform);
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#endif
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