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drm/bridge: tc358762: Program the DPI mode into the chip

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The autodetection of resolution/timing by the TC358762 can lead
to the display being shifted by a pixel or two.

Program the TC358762 with the requested mode timing so that
it can reproduce it accurately.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
This commit is contained in:
Dave Stevenson
2024-01-09 17:37:00 +00:00
committed by Dom Cobley
parent 56abeaa3b7
commit c729ac041d
1 changed files with 15 additions and 0 deletions
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15
drivers/gpu/drm/bridge/tc358762.c
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@@ -53,6 +53,12 @@
#define LCDCTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */ #define LCDCTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */
#define LCDCTRL_VSDELAY(v) (((v) & 0xfff) << 20) /* VSYNC delay */ #define LCDCTRL_VSDELAY(v) (((v) & 0xfff) << 20) /* VSYNC delay */
/* First parameter is in the 16bits, second is in the top 16bits */
#define LCD_HS_HBP 0x0424
#define LCD_HDISP_HFP 0x0428
#define LCD_VS_VBP 0x042c
#define LCD_VDISP_VFP 0x0430
/* SPI Master Registers */ /* SPI Master Registers */
#define SPICMR 0x0450 #define SPICMR 0x0450
#define SPITCR 0x0454 #define SPITCR 0x0454
@@ -139,6 +145,15 @@ static int tc358762_init(struct tc358762 *ctx)
tc358762_write(ctx, LCDCTRL, lcdctrl); tc358762_write(ctx, LCDCTRL, lcdctrl);
tc358762_write(ctx, SYSCTRL, 0x040f); tc358762_write(ctx, SYSCTRL, 0x040f);
tc358762_write(ctx, LCD_HS_HBP, (ctx->mode.hsync_end - ctx->mode.hsync_start) |
((ctx->mode.htotal - ctx->mode.hsync_end) << 16));
tc358762_write(ctx, LCD_HDISP_HFP, ctx->mode.hdisplay |
((ctx->mode.hsync_start - ctx->mode.hdisplay) << 16));
tc358762_write(ctx, LCD_VS_VBP, (ctx->mode.vsync_end - ctx->mode.vsync_start) |
((ctx->mode.vtotal - ctx->mode.vsync_end) << 16));
tc358762_write(ctx, LCD_VDISP_VFP, ctx->mode.vdisplay |
((ctx->mode.vsync_start - ctx->mode.vdisplay) << 16));
msleep(100); msleep(100);
tc358762_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION); tc358762_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION);