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drm/amd/display: Change some variable name of psr

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Panel Replay feature may also use the same variable with PSR.
Change the variable name and make it not specify for PSR.

Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tom Chung
2024-10-29 15:38:16 +08:00
committed by Alex Deucher
parent 90eacfb7ef
commit c7fafb7a46
4 changed files with 14 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View File

@@ -6790,7 +6790,7 @@ create_stream_for_sink(struct drm_connector *connector,
if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22)
tf = TRANSFER_FUNC_GAMMA_22; tf = TRANSFER_FUNC_GAMMA_22;
mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; aconnector->sr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
} }
finish: finish:
@@ -9047,7 +9047,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
* during the PSR-SU was disabled. * during the PSR-SU was disabled.
*/ */
if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
acrtc_attach->dm_irq_params.allow_psr_entry && acrtc_attach->dm_irq_params.allow_sr_entry &&
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
!amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
#endif #endif
@@ -9282,27 +9282,27 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
} }
} }
/* Decrement skip count when PSR is enabled and we're doing fast updates. */ /* Decrement skip count when SR is enabled and we're doing fast updates. */
if (acrtc_state->update_type == UPDATE_TYPE_FAST && if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
acrtc_state->stream->link->psr_settings.psr_feature_enabled) { acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
struct amdgpu_dm_connector *aconn = struct amdgpu_dm_connector *aconn =
(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
if (aconn->psr_skip_count > 0) if (aconn->sr_skip_count > 0)
aconn->psr_skip_count--; aconn->sr_skip_count--;
/* Allow PSR when skip count is 0. */ /* Allow SR when skip count is 0. */
acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count; acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count;
/* /*
* If sink supports PSR SU, there is no need to rely on * If sink supports PSR SU/Panel Replay, there is no need to rely on
* a vblank event disable request to enable PSR. PSR SU * a vblank event disable request to enable PSR/RP. PSR SU/RP
* can be enabled immediately once OS demonstrates an * can be enabled immediately once OS demonstrates an
* adequate number of fast atomic commits to notify KMD * adequate number of fast atomic commits to notify KMD
* of update events. See `vblank_control_worker()`. * of update events. See `vblank_control_worker()`.
*/ */
if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
acrtc_attach->dm_irq_params.allow_psr_entry && acrtc_attach->dm_irq_params.allow_sr_entry &&
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
!amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
#endif #endif
@@ -9313,7 +9313,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
500000000) 500000000)
amdgpu_dm_psr_enable(acrtc_state->stream); amdgpu_dm_psr_enable(acrtc_state->stream);
} else { } else {
acrtc_attach->dm_irq_params.allow_psr_entry = false; acrtc_attach->dm_irq_params.allow_sr_entry = false;
} }
mutex_unlock(&dm->dc_lock); mutex_unlock(&dm->dc_lock);

2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
View File

@@ -727,7 +727,7 @@ struct amdgpu_dm_connector {
/* Cached display modes */ /* Cached display modes */
struct drm_display_mode freesync_vid_base; struct drm_display_mode freesync_vid_base;
int psr_skip_count; int sr_skip_count;
bool disallow_edp_enter_psr; bool disallow_edp_enter_psr;
/* Record progress status of mst*/ /* Record progress status of mst*/

2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
View File

@@ -268,7 +268,7 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
if (vblank_work->stream && vblank_work->stream->link) { if (vblank_work->stream && vblank_work->stream->link) {
amdgpu_dm_crtc_set_panel_sr_feature( amdgpu_dm_crtc_set_panel_sr_feature(
vblank_work, vblank_work->enable, vblank_work, vblank_work->enable,
vblank_work->acrtc->dm_irq_params.allow_psr_entry || vblank_work->acrtc->dm_irq_params.allow_sr_entry ||
vblank_work->stream->link->replay_settings.replay_feature_enabled); vblank_work->stream->link->replay_settings.replay_feature_enabled);
} }

2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h
View File

@@ -33,7 +33,7 @@ struct dm_irq_params {
struct mod_vrr_params vrr_params; struct mod_vrr_params vrr_params;
struct dc_stream_state *stream; struct dc_stream_state *stream;
int active_planes; int active_planes;
bool allow_psr_entry; bool allow_sr_entry;
struct mod_freesync_config freesync_config; struct mod_freesync_config freesync_config;
#ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS