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drm/vc4: crtc: Add function to compute FIFO level bits

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The longer FIFOs in vc5 pixelvalves means that the FIFO full level
doesn't fit in the original register field and that we also have a
secondary field. In order to prepare for this, let's move the registers
fill part to a helper function.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
This commit is contained in:
Maxime Ripard
2020-01-13 13:40:37 +01:00
committed by popcornmix
parent 6a1c0aac75
commit cabd84dd93
1 changed files with 9 additions and 2 deletions
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11
drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -278,6 +278,14 @@ static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
}
}
static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc,
u32 format)
{
u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
return VC4_SET_FIELD(level & 0x3f,
PV_CONTROL_FIFO_LEVEL);
}
/*
* Returns the encoder attached to the CRTC.
*
@@ -378,9 +386,8 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
CRTC_WRITE(PV_CONTROL,
vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
VC4_SET_FIELD(vc4_get_fifo_full_level(vc4_crtc, format),
PV_CONTROL_FIFO_LEVEL) |
VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
PV_CONTROL_CLR_AT_START |
PV_CONTROL_TRIGGER_UNDERFLOW |