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riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree

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The D1/D1s SoCs support xtheadvector so it can be included in the
devicetree. Also include vlenb for the cpu.

Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-3-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Charlie Jenkins
2024-11-13 18:21:09 -08:00
committed by Palmer Dabbelt
parent bf6279b38a
commit ce1daeeba6
1 changed files with 2 additions and 1 deletions
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3
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
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@@ -27,7 +27,8 @@
riscv,isa = "rv64imafdc"; riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm"; "zifencei", "zihpm", "xtheadvector";
thead,vlenb = <128>;
#cooling-cells = <2>; #cooling-cells = <2>;
cpu0_intc: interrupt-controller { cpu0_intc: interrupt-controller {