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arm64: dts: imx8q: add PCIe EP for i.MX8QM and i.MX8QXP
Add PCIe EP support for i.MX8QM and i.MX8QXP. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@@ -80,6 +80,25 @@ hsio_subsys: bus@5f000000 {
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status = "disabled";
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};
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pcieb_ep: pcie-ep@5f010000 {
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compatible = "fsl,imx8q-pcie-ep";
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reg = <0x5f010000 0x00010000>,
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<0x80000000 0x10000000>;
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reg-names = "dbi", "addr_space";
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num-lanes = <1>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "dma";
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clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>,
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<&pcieb_lpcg IMX_LPCG_CLK_4>,
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<&pcieb_lpcg IMX_LPCG_CLK_5>;
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clock-names = "dbi", "mstr", "slv";
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power-domains = <&pd IMX_SC_R_PCIE_B>;
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fsl,max-link-speed = <3>;
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num-ib-windows = <6>;
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num-ob-windows = <6>;
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status = "disabled";
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};
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pcieb_lpcg: clock-controller@5f060000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5f060000 0x10000>;
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@@ -42,6 +42,25 @@
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status = "disabled";
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};
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pciea_ep: pcie-ep@5f000000 {
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compatible = "fsl,imx8q-pcie-ep";
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reg = <0x5f000000 0x00010000>,
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<0x40000000 0x10000000>;
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reg-names = "dbi", "addr_space";
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num-lanes = <1>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "dma";
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clocks = <&pciea_lpcg IMX_LPCG_CLK_6>,
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<&pciea_lpcg IMX_LPCG_CLK_4>,
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<&pciea_lpcg IMX_LPCG_CLK_5>;
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clock-names = "dbi", "mstr", "slv";
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power-domains = <&pd IMX_SC_R_PCIE_A>;
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fsl,max-link-speed = <3>;
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num-ib-windows = <6>;
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num-ob-windows = <6>;
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status = "disabled";
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};
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pcieb: pcie@5f010000 {
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compatible = "fsl,imx8q-pcie";
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reg = <0x5f010000 0x10000>,
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