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drm/amd/display: enable hostvm based on roimmu active for dcn2.1

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[ Upstream commit 48d92e8eda ]

Enabling hostvm when ROIMMU is not active seems to break GPUVM.
This fixes the issue by not enabling hostvm if ROIMMU is not
activated.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Dmytro Laktyushkin
2019-10-02 15:19:41 -04:00
committed by Greg Kroah-Hartman
parent 8f3ce0fa82
commit d4b13a1004
1 changed files with 25 additions and 15 deletions
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40
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
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@@ -22,6 +22,7 @@
* Authors: AMD * Authors: AMD
* *
*/ */
#include <linux/delay.h>
#include "dm_services.h" #include "dm_services.h"
#include "dcn20/dcn20_hubbub.h" #include "dcn20/dcn20_hubbub.h"
#include "dcn21_hubbub.h" #include "dcn21_hubbub.h"
@@ -71,30 +72,39 @@ static uint32_t convert_and_clamp(
void dcn21_dchvm_init(struct hubbub *hubbub) void dcn21_dchvm_init(struct hubbub *hubbub)
{ {
struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
uint32_t riommu_active;
int i;
//Init DCHVM block //Init DCHVM block
REG_UPDATE(DCHVM_CTRL0, HOSTVM_INIT_REQ, 1); REG_UPDATE(DCHVM_CTRL0, HOSTVM_INIT_REQ, 1);
//Poll until RIOMMU_ACTIVE = 1 //Poll until RIOMMU_ACTIVE = 1
//TODO: Figure out interval us and retry count for (i = 0; i < 100; i++) {
REG_WAIT(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, 1, 5, 100); REG_GET(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, &riommu_active);
//Reflect the power status of DCHUBBUB if (riommu_active)
REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1); break;
else
udelay(5);
}
//Start rIOMMU prefetching if (riommu_active) {
REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1); //Reflect the power status of DCHUBBUB
REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1);
// Enable dynamic clock gating //Start rIOMMU prefetching
REG_UPDATE_4(DCHVM_CLK_CTRL, REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1);
HVM_DISPCLK_R_GATE_DIS, 0,
HVM_DISPCLK_G_GATE_DIS, 0,
HVM_DCFCLK_R_GATE_DIS, 0,
HVM_DCFCLK_G_GATE_DIS, 0);
//Poll until HOSTVM_PREFETCH_DONE = 1 // Enable dynamic clock gating
//TODO: Figure out interval us and retry count REG_UPDATE_4(DCHVM_CLK_CTRL,
REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100); HVM_DISPCLK_R_GATE_DIS, 0,
HVM_DISPCLK_G_GATE_DIS, 0,
HVM_DCFCLK_R_GATE_DIS, 0,
HVM_DCFCLK_G_GATE_DIS, 0);
//Poll until HOSTVM_PREFETCH_DONE = 1
REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);
}
} }
static int hubbub21_init_dchub(struct hubbub *hubbub, static int hubbub21_init_dchub(struct hubbub *hubbub,