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iommu/arm-smmu: Pretty-print context fault related regs
Parse out the bitfields for easier-to-read fault messages. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Pranjal Shrivastava <praan@google.com> Link: https://lore.kernel.org/r/20240701162025.375134-4-robdclark@gmail.com Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Rob Clark
Will Deacon
@@ -383,64 +383,44 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
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struct arm_smmu_domain *smmu_domain = dev;
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struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops;
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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u32 fsr, fsynr, cbfrsynra, resume = 0;
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struct arm_smmu_context_fault_info cfi;
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u32 resume = 0;
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int idx = smmu_domain->cfg.cbndx;
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phys_addr_t phys_soft;
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unsigned long iova;
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int ret, tmp;
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static DEFINE_RATELIMIT_STATE(_rs,
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DEFAULT_RATELIMIT_INTERVAL,
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DEFAULT_RATELIMIT_BURST);
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fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
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if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
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arm_smmu_read_context_fault_info(smmu, idx, &cfi);
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if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT))
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return IRQ_NONE;
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fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
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iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
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cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
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if (list_empty(&tbu_list)) {
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ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
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fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
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ret = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova,
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cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
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if (ret == -ENOSYS)
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dev_err_ratelimited(smmu->dev,
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"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
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fsr, iova, fsynr, cbfrsynra, idx);
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arm_smmu_print_context_fault_info(smmu, idx, &cfi);
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arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
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arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr);
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return IRQ_HANDLED;
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}
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phys_soft = ops->iova_to_phys(ops, iova);
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phys_soft = ops->iova_to_phys(ops, cfi.iova);
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tmp = report_iommu_fault(&smmu_domain->domain, NULL, iova,
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fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
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tmp = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova,
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cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
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if (!tmp || tmp == -EBUSY) {
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ret = IRQ_HANDLED;
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resume = ARM_SMMU_RESUME_TERMINATE;
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} else {
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phys_addr_t phys_atos = qcom_smmu_verify_fault(smmu_domain, iova, fsr);
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phys_addr_t phys_atos = qcom_smmu_verify_fault(smmu_domain, cfi.iova, cfi.fsr);
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if (__ratelimit(&_rs)) {
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dev_err(smmu->dev,
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"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
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fsr, iova, fsynr, cbfrsynra, idx);
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dev_err(smmu->dev,
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"FSR = %08x [%s%s%s%s%s%s%s%s%s], SID=0x%x\n",
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fsr,
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(fsr & 0x02) ? "TF " : "",
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(fsr & 0x04) ? "AFF " : "",
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(fsr & 0x08) ? "PF " : "",
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(fsr & 0x10) ? "EF " : "",
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(fsr & 0x20) ? "TLBMCF " : "",
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(fsr & 0x40) ? "TLBLKF " : "",
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(fsr & 0x80) ? "MHF " : "",
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(fsr & 0x40000000) ? "SS " : "",
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(fsr & 0x80000000) ? "MULTI " : "",
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cbfrsynra);
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arm_smmu_print_context_fault_info(smmu, idx, &cfi);
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dev_err(smmu->dev,
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"soft iova-to-phys=%pa\n", &phys_soft);
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@@ -474,10 +454,10 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
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*/
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if (tmp != -EBUSY) {
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/* Clear the faulting FSR */
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arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
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arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr);
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/* Retry or terminate any stalled transactions */
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if (fsr & ARM_SMMU_CB_FSR_SS)
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if (cfi.fsr & ARM_SMMU_CB_FSR_SS)
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arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME, resume);
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}
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@@ -405,32 +405,72 @@ static const struct iommu_flush_ops arm_smmu_s2_tlb_ops_v1 = {
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.tlb_add_page = arm_smmu_tlb_add_page_s2_v1,
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};
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void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx,
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struct arm_smmu_context_fault_info *cfi)
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{
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cfi->iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
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cfi->fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
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cfi->fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
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cfi->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
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}
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void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx,
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const struct arm_smmu_context_fault_info *cfi)
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{
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dev_dbg(smmu->dev,
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"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
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cfi->fsr, cfi->iova, cfi->fsynr, cfi->cbfrsynra, idx);
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dev_err(smmu->dev, "FSR = %08x [%s%sFormat=%u%s%s%s%s%s%s%s%s], SID=0x%x\n",
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cfi->fsr,
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(cfi->fsr & ARM_SMMU_CB_FSR_MULTI) ? "MULTI " : "",
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(cfi->fsr & ARM_SMMU_CB_FSR_SS) ? "SS " : "",
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(u32)FIELD_GET(ARM_SMMU_CB_FSR_FORMAT, cfi->fsr),
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(cfi->fsr & ARM_SMMU_CB_FSR_UUT) ? " UUT" : "",
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(cfi->fsr & ARM_SMMU_CB_FSR_ASF) ? " ASF" : "",
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(cfi->fsr & ARM_SMMU_CB_FSR_TLBLKF) ? " TLBLKF" : "",
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(cfi->fsr & ARM_SMMU_CB_FSR_TLBMCF) ? " TLBMCF" : "",
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(cfi->fsr & ARM_SMMU_CB_FSR_EF) ? " EF" : "",
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(cfi->fsr & ARM_SMMU_CB_FSR_PF) ? " PF" : "",
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(cfi->fsr & ARM_SMMU_CB_FSR_AFF) ? " AFF" : "",
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(cfi->fsr & ARM_SMMU_CB_FSR_TF) ? " TF" : "",
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cfi->cbfrsynra);
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dev_err(smmu->dev, "FSYNR0 = %08x [S1CBNDX=%u%s%s%s%s%s%s PLVL=%u]\n",
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cfi->fsynr,
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(u32)FIELD_GET(ARM_SMMU_CB_FSYNR0_S1CBNDX, cfi->fsynr),
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(cfi->fsynr & ARM_SMMU_CB_FSYNR0_AFR) ? " AFR" : "",
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(cfi->fsynr & ARM_SMMU_CB_FSYNR0_PTWF) ? " PTWF" : "",
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(cfi->fsynr & ARM_SMMU_CB_FSYNR0_NSATTR) ? " NSATTR" : "",
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(cfi->fsynr & ARM_SMMU_CB_FSYNR0_IND) ? " IND" : "",
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(cfi->fsynr & ARM_SMMU_CB_FSYNR0_PNU) ? " PNU" : "",
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(cfi->fsynr & ARM_SMMU_CB_FSYNR0_WNR) ? " WNR" : "",
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(u32)FIELD_GET(ARM_SMMU_CB_FSYNR0_PLVL, cfi->fsynr));
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}
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static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
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{
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u32 fsr, fsynr, cbfrsynra;
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unsigned long iova;
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struct arm_smmu_context_fault_info cfi;
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struct arm_smmu_domain *smmu_domain = dev;
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
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DEFAULT_RATELIMIT_BURST);
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int idx = smmu_domain->cfg.cbndx;
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int ret;
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fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
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if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
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arm_smmu_read_context_fault_info(smmu, idx, &cfi);
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if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT))
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return IRQ_NONE;
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fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
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iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
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cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
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ret = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova,
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cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
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ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
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fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
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if (ret == -ENOSYS && __ratelimit(&rs))
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arm_smmu_print_context_fault_info(smmu, idx, &cfi);
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if (ret == -ENOSYS)
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dev_err_ratelimited(smmu->dev,
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"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
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fsr, iova, fsynr, cbfrsynra, idx);
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arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
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arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr);
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return IRQ_HANDLED;
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}
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@@ -198,6 +198,7 @@ enum arm_smmu_cbar_type {
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#define ARM_SMMU_CB_FSR 0x58
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#define ARM_SMMU_CB_FSR_MULTI BIT(31)
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#define ARM_SMMU_CB_FSR_SS BIT(30)
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#define ARM_SMMU_CB_FSR_FORMAT GENMASK(10, 9)
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#define ARM_SMMU_CB_FSR_UUT BIT(8)
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#define ARM_SMMU_CB_FSR_ASF BIT(7)
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#define ARM_SMMU_CB_FSR_TLBLKF BIT(6)
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@@ -223,7 +224,14 @@ enum arm_smmu_cbar_type {
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#define ARM_SMMU_CB_FAR 0x60
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#define ARM_SMMU_CB_FSYNR0 0x68
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#define ARM_SMMU_CB_FSYNR0_PLVL GENMASK(1, 0)
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#define ARM_SMMU_CB_FSYNR0_WNR BIT(4)
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#define ARM_SMMU_CB_FSYNR0_PNU BIT(5)
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#define ARM_SMMU_CB_FSYNR0_IND BIT(6)
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#define ARM_SMMU_CB_FSYNR0_NSATTR BIT(8)
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#define ARM_SMMU_CB_FSYNR0_PTWF BIT(10)
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#define ARM_SMMU_CB_FSYNR0_AFR BIT(11)
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#define ARM_SMMU_CB_FSYNR0_S1CBNDX GENMASK(23, 16)
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#define ARM_SMMU_CB_FSYNR1 0x6c
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@@ -533,4 +541,17 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu);
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void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx);
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int arm_mmu500_reset(struct arm_smmu_device *smmu);
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struct arm_smmu_context_fault_info {
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unsigned long iova;
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u32 fsr;
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u32 fsynr;
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u32 cbfrsynra;
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};
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void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx,
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struct arm_smmu_context_fault_info *cfi);
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void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx,
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const struct arm_smmu_context_fault_info *cfi);
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#endif /* _ARM_SMMU_H */
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