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dt-bindings: memory: lpddr3: adjust IO width to spec

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According to JEDEC Standard No. 209-3 (table 3.4.1 "Mode Register
Assignment and Definition in LPDDR3 SDRAM"), the LPDDR3 supports only
16- and 32-bit IO width.  Drop the unsupported others.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220206135807.211767-5-krzysztof.kozlowski@canonical.com
This commit is contained in:
Krzysztof Kozlowski
2022-02-06 14:58:03 +01:00
parent 28f818580e
commit d98e72b6f9
1 changed files with 0 additions and 2 deletions
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2
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
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@@ -34,10 +34,8 @@ properties:
description: |
IO bus width in bits of SDRAM chip.
enum:
- 64
- 32
- 16
- 8
manufacturer-id:
$ref: /schemas/types.yaml#/definitions/uint32