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drm/rp1: rp1-dsi: Add support for inverting lane polarities

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The D-PHY on RP1 support lane polarity swapping, and there
is a standard device tree mechanism for configuring this,
so tie the two together.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
This commit is contained in:
Dave Stevenson
2025-09-25 13:07:52 +01:00
committed by Dom Cobley
parent da26ad1a5f
commit dab82cdd1c
3 changed files with 24 additions and 1 deletions
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10
drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.c
View File

@@ -419,9 +419,11 @@ static const struct mipi_dsi_host_ops rp1dsi_mipi_dsi_host_ops = {
static int rp1dsi_platform_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
struct device_node *endpoint;
struct drm_device *drm;
struct rp1_dsi *dsi;
int i, ret;
int i, nr_lanes, ret;
drm = drm_dev_alloc(&rp1dsi_driver, dev);
if (IS_ERR(drm)) {
@@ -461,6 +463,12 @@ static int rp1dsi_platform_probe(struct platform_device *pdev)
}
}
endpoint = of_graph_get_endpoint_by_regs(node, 0, -1);
nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
if (nr_lanes > 0 && nr_lanes <= 4)
of_property_read_u32_array(endpoint, "lane-polarities",
dsi->lane_polarities, nr_lanes + 1);
for (i = 0; i < RP1DSI_NUM_HW_BLOCKS; i++) {
dsi->hw_base[i] =
devm_ioremap_resource(dev,

3
drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.h
View File

@@ -49,6 +49,9 @@ struct rp1_dsi {
/* Clocks. We need DPI clock; the others are frequency references */
struct clk *clocks[RP1DSI_NUM_CLOCKS];
/* Device tree parsed information */
u32 lane_polarities[5];
/* Block (DSI DMA, DSI Host) base addresses, and current state */
void __iomem *hw_base[RP1DSI_NUM_HW_BLOCKS];
u32 cur_fmt;

12
drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c
View File

@@ -143,7 +143,12 @@
#define DPHY_PLL_INPUT_DIV_OFFSET 0x17
#define DPHY_PLL_LOOP_DIV_OFFSET 0x18
#define DPHY_PLL_DIV_CTRL_OFFSET 0x19
#define DPHY_CLK_PN_SWAP 0x35
#define DPHY_HS_RX_CTRL_LANE0_OFFSET 0x44
#define DPHY_D0_PN_SWAP 0x45
#define DPHY_D1_PN_SWAP 0x55
#define DPHY_D2_PN_SWAP 0x85
#define DPHY_D3_PN_SWAP 0x95
#define DSI_WRITE(reg, val) writel((val), dsi->hw_base[RP1DSI_HW_BLOCK_DSI] + (reg))
@@ -354,6 +359,13 @@ static u32 dphy_init(struct rp1_dsi *dsi, u32 ref_freq, u32 vco_freq)
udelay(1);
/* Since we are in DSI (not CSI2) mode here, start the PLL */
actual_vco_freq = dphy_configure_pll(dsi, ref_freq, vco_freq);
dphy_transaction(dsi, DPHY_CLK_PN_SWAP, !!dsi->lane_polarities[0]);
dphy_transaction(dsi, DPHY_D0_PN_SWAP, !!dsi->lane_polarities[1]);
dphy_transaction(dsi, DPHY_D1_PN_SWAP, !!dsi->lane_polarities[2]);
dphy_transaction(dsi, DPHY_D2_PN_SWAP, !!dsi->lane_polarities[3]);
dphy_transaction(dsi, DPHY_D3_PN_SWAP, !!dsi->lane_polarities[4]);
udelay(1);
/* Unreset */
DSI_WRITE(DSI_PHYRSTZ, DSI_PHYRSTZ_SHUTDOWNZ_BITS);