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clk-bcm2835: Use PLLD for DSI0 HS clock

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DSI0 can take the clock from either PLLA or PLLD. PLLA is
the default muxing, but PLLD is considered the more stable.

Switch to using PLLD.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
This commit is contained in:
Dave Stevenson
2024-04-26 17:05:39 +01:00
committed by Dom Cobley
parent f9f70d75be
commit de24342cef
1 changed files with 4 additions and 0 deletions
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4
drivers/clk/bcm/clk-bcm2835.c
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@@ -107,6 +107,7 @@
#define CM_UARTDIV 0x0f4
#define CM_VECCTL 0x0f8
#define CM_VECDIV 0x0fc
#define CM_DSI0HSCK 0x120
#define CM_PULSECTL 0x190
#define CM_PULSEDIV 0x194
#define CM_SDCCTL 0x1a8
@@ -2357,6 +2358,9 @@ static int bcm2835_clk_probe(struct platform_device *pdev)
if (IS_ERR(cprman->regs))
return PTR_ERR(cprman->regs);
/* Mux DSI0 clock to PLLD */
cprman_write(cprman, CM_DSI0HSCK, 1);
fw_node = of_parse_phandle(dev->of_node, "firmware", 0);
if (fw_node) {
struct rpi_firmware *fw = rpi_firmware_get(fw_node);