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usb: dwc3: core: add support for setting NAK enhancement bits for FS/HS

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If a device frequently NAKs, it can exhaust the scheduled handshakes in
a frame. It will then not get polled by the controller until the next
frame interval. This is most noticeable on FS devices as the controller
schedules a small set of transactions only once per full-speed frame.

Setting the ENH_PER_NAK_FS/LS bits in the GUCTL1 register increases the
number of transactions that can be scheduled to Async (Control/Bulk)
endpoints in the respective frame time. In the FS case, this only
applies to FS devices directly connected to root ports.

Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
This commit is contained in:
Jonathan Bell
2024-11-06 10:45:24 +00:00
committed by Dom Cobley
parent 8e09fbe2b7
commit ec5a9f71e5
2 changed files with 16 additions and 0 deletions
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10
drivers/usb/dwc3/core.c
View File

@@ -1481,6 +1481,12 @@ static int dwc3_core_init(struct dwc3 *dwc)
if (dwc->dis_tx_ipgap_linecheck_quirk)
reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
if (dwc->enh_nak_fs_quirk)
reg |= DWC3_GUCTL1_NAK_PER_ENH_FS;
if (dwc->enh_nak_hs_quirk)
reg |= DWC3_GUCTL1_NAK_PER_ENH_HS;
if (dwc->parkmode_disable_ss_quirk)
reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
@@ -1865,6 +1871,10 @@ static void dwc3_get_properties(struct dwc3 *dwc)
"snps,resume-hs-terminations");
dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
"snps,ulpi-ext-vbus-drv");
dwc->enh_nak_fs_quirk = device_property_read_bool(dev,
"snps,enhanced-nak-fs-quirk");
dwc->enh_nak_hs_quirk = device_property_read_bool(dev,
"snps,enhanced-nak-hs-quirk");
dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
"snps,parkmode-disable-ss-quirk");
dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev,

6
drivers/usb/dwc3/core.h
View File

@@ -282,6 +282,8 @@
#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26)
#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
#define DWC3_GUCTL1_NAK_PER_ENH_FS BIT(19)
#define DWC3_GUCTL1_NAK_PER_ENH_HS BIT(18)
#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
#define DWC3_GUCTL1_PARKMODE_DISABLE_HS BIT(16)
#define DWC3_GUCTL1_PARKMODE_DISABLE_FSLS BIT(15)
@@ -1140,6 +1142,8 @@ struct dwc3_scratchpad_array {
* generation after resume from suspend.
* @ulpi_ext_vbus_drv: Set to confiure the upli chip to drives CPEN pin
* VBUS with an external supply.
* @enh_nak_fs_quirk: Set to schedule more handshakes to Async FS endpoints.
* @enh_nak_hs_quirk: Set to schedule more handshakes to Async HS endpoints.
* @parkmode_disable_ss_quirk: If set, disable park mode feature for all
* Superspeed instances.
* @parkmode_disable_hs_quirk: If set, disable park mode feature for all
@@ -1384,6 +1388,8 @@ struct dwc3 {
unsigned dis_tx_ipgap_linecheck_quirk:1;
unsigned resume_hs_terminations:1;
unsigned ulpi_ext_vbus_drv:1;
unsigned enh_nak_fs_quirk:1;
unsigned enh_nak_hs_quirk:1;
unsigned parkmode_disable_ss_quirk:1;
unsigned parkmode_disable_hs_quirk:1;
unsigned parkmode_disable_fsls_quirk:1;