From f10106dda2713eeaf1df308e25f1f04c57d3e51a Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Fri, 26 Apr 2024 19:20:41 +0100 Subject: [PATCH] drm/panel-simple: Increase pixel clock on Pi 7inch panel The Toshiba bridge is very fussy and doesn't like the CM3 output when being told to produce a 27.777MHz pixel clock, which is an almost perfect match to the DSI link integer divider. Increasing to 30MHz will switch the DSI link from 333MHz to 400MHz and makes the bridge happy with the same video timing as works on Pi4. (Pi4 will be using a link frequency of 375MHz due to a 3GHz parent PLL). Signed-off-by: Dave Stevenson --- drivers/gpu/drm/panel/panel-simple.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index ea0795fd6475..df4181525b17 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -3821,11 +3821,11 @@ static const struct panel_desc rocktech_rk043fn48h = { }; static const struct drm_display_mode raspberrypi_7inch_mode = { - .clock = 27777, + .clock = 30000, .hdisplay = 800, - .hsync_start = 800 + 59, - .hsync_end = 800 + 59 + 2, - .htotal = 800 + 59 + 2 + 45, + .hsync_start = 800 + 131, + .hsync_end = 800 + 131 + 2, + .htotal = 800 + 131 + 2 + 45, .vdisplay = 480, .vsync_start = 480 + 7, .vsync_end = 480 + 7 + 2,