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clk-bcm2835: Disable v3d clock

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This is controlled by firmware, see clk-raspberrypi.c

Signed-off-by: popcornmix <popcornmix@gmail.com>

clk-bcm2835: Remove VEC clock support

Signed-off-by: Dom Cobley <popcornmix@gmail.com>
This commit is contained in:
popcornmix
2019-09-03 20:28:00 +01:00
committed by Dom Cobley
parent 4e5bd75bbf
commit f9f70d75be
1 changed files with 12 additions and 33 deletions
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45
drivers/clk/bcm/clk-bcm2835.c
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@@ -1769,16 +1769,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
.hold_mask = CM_PLLA_HOLDCORE, .hold_mask = CM_PLLA_HOLDCORE,
.fixed_divider = 1, .fixed_divider = 1,
.flags = CLK_SET_RATE_PARENT), .flags = CLK_SET_RATE_PARENT),
[BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
SOC_ALL, /*
.name = "plla_per", * PLLA_PER is used for gpu clocks. Controlled by firmware, see
.source_pll = "plla", * clk-raspberrypi.c.
.cm_reg = CM_PLLA, */
.a2w_reg = A2W_PLLA_PER,
.load_mask = CM_PLLA_LOADPER,
.hold_mask = CM_PLLA_HOLDPER,
.fixed_divider = 1,
.flags = CLK_SET_RATE_PARENT),
[BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
SOC_ALL, SOC_ALL,
.name = "plla_dsi0", .name = "plla_dsi0",
@@ -2079,14 +2075,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
.int_bits = 6, .int_bits = 6,
.frac_bits = 0, .frac_bits = 0,
.tcnt_mux = 3), .tcnt_mux = 3),
[BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
SOC_ALL, /*
.name = "v3d", * CLOCK_V3D is used for v3d clock. Controlled by firmware, see
.ctl_reg = CM_V3DCTL, * clk-raspberrypi.c.
.div_reg = CM_V3DDIV, */
.int_bits = 4,
.frac_bits = 8,
.tcnt_mux = 4),
/* /*
* VPU clock. This doesn't have an enable bit, since it drives * VPU clock. This doesn't have an enable bit, since it drives
* the bus for everything else, and is special so it doesn't need * the bus for everything else, and is special so it doesn't need
@@ -2249,21 +2243,6 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
.tcnt_mux = 28, .tcnt_mux = 28,
.round_up = true), .round_up = true),
/* TV encoder clock. Only operating frequency is 108Mhz. */
[BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
SOC_ALL,
.name = "vec",
.ctl_reg = CM_VECCTL,
.div_reg = CM_VECDIV,
.int_bits = 4,
.frac_bits = 0,
/*
* Allow rate change propagation only on PLLH_AUX which is
* assigned index 7 in the parent array.
*/
.set_rate_parent = BIT(7),
.tcnt_mux = 29),
/* dsi clocks */ /* dsi clocks */
[BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
SOC_ALL, SOC_ALL,