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clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock

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The VEC clock requires needs to be set at exactly 108MHz. Allow rate
change propagation on PLLH_AUX to match this requirement wihtout
impacting other IPs (PLLH is currently only used by the HDMI encoder,
which cannot be enabled when the VEC encoder is enabled).

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from commit d86d46af84)
This commit is contained in:
Boris Brezillon
2016-12-01 22:00:20 +01:00
committed by Eric Anholt
parent 68938266ba
commit fd23822108
1 changed files with 6 additions and 1 deletions
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7
drivers/clk/bcm/clk-bcm2835.c
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@@ -1920,7 +1920,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
.ctl_reg = CM_VECCTL, .ctl_reg = CM_VECCTL,
.div_reg = CM_VECDIV, .div_reg = CM_VECDIV,
.int_bits = 4, .int_bits = 4,
.frac_bits = 0), .frac_bits = 0,
/*
* Allow rate change propagation only on PLLH_AUX which is
* assigned index 7 in the parent array.
*/
.set_rate_parent = BIT(7)),
/* dsi clocks */ /* dsi clocks */
[BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(