mirror of
https://github.com/raspberrypi/linux.git
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Merge tag 'for-linus' of https://github.com/openrisc/linux
Pull OpenRISC updates from Stafford Horne: - Added support for restartable sequences (me) - Migration to Generic built-in DTB (Masahiro Yamada) * tag 'for-linus' of https://github.com/openrisc/linux: rseq/selftests: Add support for OpenRISC openrisc: Add support for restartable sequences openrisc: Add HAVE_REGS_AND_STACK_ACCESS_API support openrisc: migrate to the generic rule for built-in DTB
This commit is contained in:
Linus Torvalds
@@ -226,8 +226,32 @@ unsigned int yield_mod_cnt, nr_abort;
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"addi " INJECT_ASM_REG "," INJECT_ASM_REG ", -1\n\t" \
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"bnez " INJECT_ASM_REG ", 222b\n\t" \
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"333:\n\t"
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#elif defined(__or1k__)
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#define RSEQ_INJECT_INPUT \
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, [loop_cnt_1]"m"(loop_cnt[1]) \
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, [loop_cnt_2]"m"(loop_cnt[2]) \
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, [loop_cnt_3]"m"(loop_cnt[3]) \
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, [loop_cnt_4]"m"(loop_cnt[4]) \
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, [loop_cnt_5]"m"(loop_cnt[5]) \
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, [loop_cnt_6]"m"(loop_cnt[6])
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#define INJECT_ASM_REG "r31"
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#define RSEQ_INJECT_CLOBBER \
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, INJECT_ASM_REG
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#define RSEQ_INJECT_ASM(n) \
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"l.lwz " INJECT_ASM_REG ", %[loop_cnt_" #n "]\n\t" \
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"l.sfeqi " INJECT_ASM_REG ", 0\n\t" \
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"l.bf 333f\n\t" \
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" l.nop\n\t" \
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"222:\n\t" \
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"l.addi " INJECT_ASM_REG "," INJECT_ASM_REG ", -1\n\t" \
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"l.sfeqi " INJECT_ASM_REG ", 0\n\t" \
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"l.bf 222f\n\t" \
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" l.nop\n\t" \
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"333:\n\t"
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#else
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#error unsupported target
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#endif
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412
tools/testing/selftests/rseq/rseq-or1k-bits.h
Normal file
412
tools/testing/selftests/rseq/rseq-or1k-bits.h
Normal file
@@ -0,0 +1,412 @@
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/* SPDX-License-Identifier: LGPL-2.1 OR MIT */
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#include "rseq-bits-template.h"
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#if defined(RSEQ_TEMPLATE_MO_RELAXED) && \
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(defined(RSEQ_TEMPLATE_CPU_ID) || defined(RSEQ_TEMPLATE_MM_CID))
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static inline __always_inline
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int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv,
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int cpu)
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{
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RSEQ_INJECT_C(9)
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__asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f)
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RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]")
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#ifdef RSEQ_COMPARE_TWICE
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RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]")
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RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]")
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#endif
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RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs)
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RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f)
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RSEQ_INJECT_ASM(3)
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RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]")
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RSEQ_INJECT_ASM(4)
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#ifdef RSEQ_COMPARE_TWICE
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RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]")
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RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]")
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#endif
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RSEQ_ASM_OP_FINAL_STORE(v, newv, 3)
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RSEQ_INJECT_ASM(5)
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RSEQ_ASM_DEFINE_ABORT(4, abort)
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: /* gcc asm goto does not allow outputs */
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: [cpu_id] "r" (cpu),
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[current_cpu_id] "m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD),
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[rseq_cs] "m" (rseq_get_abi()->rseq_cs.arch.ptr),
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[v] "m" (*v),
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[expect] "r" (expect),
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[newv] "r" (newv)
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RSEQ_INJECT_INPUT
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: "memory", RSEQ_ASM_TMP_REG_1
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RSEQ_INJECT_CLOBBER
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: abort, cmpfail
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#ifdef RSEQ_COMPARE_TWICE
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, error1, error2
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#endif
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);
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return 0;
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abort:
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RSEQ_INJECT_FAILED
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return -1;
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cmpfail:
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return 1;
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#ifdef RSEQ_COMPARE_TWICE
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error1:
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rseq_bug("cpu_id comparison failed");
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error2:
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rseq_bug("expected value comparison failed");
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#endif
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}
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static inline __always_inline
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int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpnev_storeoffp_load)(intptr_t *v, intptr_t expectnot,
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off_t voffp, intptr_t *load, int cpu)
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{
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RSEQ_INJECT_C(9)
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__asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f)
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RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]")
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#ifdef RSEQ_COMPARE_TWICE
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RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]")
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RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]")
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#endif
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RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs)
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RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f)
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RSEQ_INJECT_ASM(3)
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RSEQ_ASM_OP_CMPNE(v, expectnot, "%l[cmpfail]")
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RSEQ_INJECT_ASM(4)
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#ifdef RSEQ_COMPARE_TWICE
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RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]")
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RSEQ_ASM_OP_CMPNE(v, expectnot, "%l[error2]")
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#endif
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RSEQ_ASM_OP_R_LOAD(v)
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RSEQ_ASM_OP_R_STORE(load)
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RSEQ_ASM_OP_R_LOAD_OFF(voffp)
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RSEQ_ASM_OP_R_FINAL_STORE(v, 3)
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RSEQ_INJECT_ASM(5)
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RSEQ_ASM_DEFINE_ABORT(4, abort)
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: /* gcc asm goto does not allow outputs */
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: [cpu_id] "r" (cpu),
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[current_cpu_id] "m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD),
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[rseq_cs] "m" (rseq_get_abi()->rseq_cs.arch.ptr),
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[v] "m" (*v),
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[expectnot] "r" (expectnot),
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[load] "m" (*load),
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[voffp] "Ir" (voffp)
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RSEQ_INJECT_INPUT
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: "memory", RSEQ_ASM_TMP_REG_1
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RSEQ_INJECT_CLOBBER
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: abort, cmpfail
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#ifdef RSEQ_COMPARE_TWICE
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, error1, error2
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#endif
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);
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return 0;
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abort:
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RSEQ_INJECT_FAILED
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return -1;
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cmpfail:
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return 1;
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#ifdef RSEQ_COMPARE_TWICE
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error1:
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rseq_bug("cpu_id comparison failed");
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error2:
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rseq_bug("expected value comparison failed");
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#endif
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}
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static inline __always_inline
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int RSEQ_TEMPLATE_IDENTIFIER(rseq_addv)(intptr_t *v, intptr_t count, int cpu)
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{
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RSEQ_INJECT_C(9)
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__asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f)
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#ifdef RSEQ_COMPARE_TWICE
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RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]")
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#endif
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RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs)
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RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f)
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RSEQ_INJECT_ASM(3)
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#ifdef RSEQ_COMPARE_TWICE
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RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]")
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#endif
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RSEQ_ASM_OP_R_LOAD(v)
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RSEQ_ASM_OP_R_ADD(count)
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RSEQ_ASM_OP_R_FINAL_STORE(v, 3)
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RSEQ_INJECT_ASM(4)
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RSEQ_ASM_DEFINE_ABORT(4, abort)
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: /* gcc asm goto does not allow outputs */
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: [cpu_id] "r" (cpu),
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[current_cpu_id] "m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD),
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[rseq_cs] "m" (rseq_get_abi()->rseq_cs.arch.ptr),
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[v] "m" (*v),
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[count] "r" (count)
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RSEQ_INJECT_INPUT
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: "memory", RSEQ_ASM_TMP_REG_1
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RSEQ_INJECT_CLOBBER
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: abort
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#ifdef RSEQ_COMPARE_TWICE
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, error1
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#endif
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);
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return 0;
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abort:
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RSEQ_INJECT_FAILED
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return -1;
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#ifdef RSEQ_COMPARE_TWICE
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error1:
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rseq_bug("cpu_id comparison failed");
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#endif
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}
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static inline __always_inline
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int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_cmpeqv_storev)(intptr_t *v, intptr_t expect,
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intptr_t *v2, intptr_t expect2,
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intptr_t newv, int cpu)
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{
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RSEQ_INJECT_C(9)
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__asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f)
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RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]")
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#ifdef RSEQ_COMPARE_TWICE
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RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]")
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RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]")
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RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error3]")
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#endif
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RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs)
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RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f)
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RSEQ_INJECT_ASM(3)
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RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]")
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RSEQ_INJECT_ASM(4)
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RSEQ_ASM_OP_CMPEQ(v2, expect2, "%l[cmpfail]")
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RSEQ_INJECT_ASM(5)
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#ifdef RSEQ_COMPARE_TWICE
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RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]")
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RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]")
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RSEQ_ASM_OP_CMPEQ(v2, expect2, "%l[error3]")
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#endif
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RSEQ_ASM_OP_FINAL_STORE(v, newv, 3)
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RSEQ_INJECT_ASM(6)
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RSEQ_ASM_DEFINE_ABORT(4, abort)
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: /* gcc asm goto does not allow outputs */
|
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: [cpu_id] "r" (cpu),
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[current_cpu_id] "m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD),
|
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[rseq_cs] "m" (rseq_get_abi()->rseq_cs.arch.ptr),
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[v] "m" (*v),
|
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[expect] "r" (expect),
|
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[v2] "m" (*v2),
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[expect2] "r" (expect2),
|
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[newv] "r" (newv)
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RSEQ_INJECT_INPUT
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: "memory", RSEQ_ASM_TMP_REG_1
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RSEQ_INJECT_CLOBBER
|
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: abort, cmpfail
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#ifdef RSEQ_COMPARE_TWICE
|
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, error1, error2, error3
|
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#endif
|
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);
|
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|
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return 0;
|
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abort:
|
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RSEQ_INJECT_FAILED
|
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return -1;
|
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cmpfail:
|
||||
return 1;
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#ifdef RSEQ_COMPARE_TWICE
|
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error1:
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rseq_bug("cpu_id comparison failed");
|
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error2:
|
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rseq_bug("expected value comparison failed");
|
||||
error3:
|
||||
rseq_bug("2nd expected value comparison failed");
|
||||
#endif
|
||||
}
|
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|
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#define RSEQ_ARCH_HAS_OFFSET_DEREF_ADDV
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|
||||
/*
|
||||
* pval = *(ptr+off)
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* *pval += inc;
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||||
*/
|
||||
static inline __always_inline
|
||||
int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, intptr_t inc,
|
||||
int cpu)
|
||||
{
|
||||
RSEQ_INJECT_C(9)
|
||||
|
||||
__asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f)
|
||||
#ifdef RSEQ_COMPARE_TWICE
|
||||
RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]")
|
||||
#endif
|
||||
RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs)
|
||||
RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f)
|
||||
RSEQ_INJECT_ASM(3)
|
||||
#ifdef RSEQ_COMPARE_TWICE
|
||||
RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]")
|
||||
#endif
|
||||
RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, 3)
|
||||
RSEQ_INJECT_ASM(4)
|
||||
RSEQ_ASM_DEFINE_ABORT(4, abort)
|
||||
: /* gcc asm goto does not allow outputs */
|
||||
: [cpu_id] "r" (cpu),
|
||||
[current_cpu_id] "m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD),
|
||||
[rseq_cs] "m" (rseq_get_abi()->rseq_cs.arch.ptr),
|
||||
[ptr] "r" (ptr),
|
||||
[off] "r" (off),
|
||||
[inc] "r" (inc)
|
||||
RSEQ_INJECT_INPUT
|
||||
: "memory", RSEQ_ASM_TMP_REG_1
|
||||
RSEQ_INJECT_CLOBBER
|
||||
: abort
|
||||
#ifdef RSEQ_COMPARE_TWICE
|
||||
, error1
|
||||
#endif
|
||||
);
|
||||
return 0;
|
||||
abort:
|
||||
RSEQ_INJECT_FAILED
|
||||
return -1;
|
||||
#ifdef RSEQ_COMPARE_TWICE
|
||||
error1:
|
||||
rseq_bug("cpu_id comparison failed");
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* #if defined(RSEQ_TEMPLATE_MO_RELAXED) &&
|
||||
(defined(RSEQ_TEMPLATE_CPU_ID) || defined(RSEQ_TEMPLATE_MM_CID)) */
|
||||
|
||||
#if (defined(RSEQ_TEMPLATE_MO_RELAXED) || defined(RSEQ_TEMPLATE_MO_RELEASE)) && \
|
||||
(defined(RSEQ_TEMPLATE_CPU_ID) || defined(RSEQ_TEMPLATE_MM_CID))
|
||||
|
||||
static inline __always_inline
|
||||
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trystorev_storev)(intptr_t *v, intptr_t expect,
|
||||
intptr_t *v2, intptr_t newv2,
|
||||
intptr_t newv, int cpu)
|
||||
{
|
||||
RSEQ_INJECT_C(9)
|
||||
|
||||
__asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f)
|
||||
RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]")
|
||||
#ifdef RSEQ_COMPARE_TWICE
|
||||
RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]")
|
||||
RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]")
|
||||
#endif
|
||||
RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs)
|
||||
RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f)
|
||||
RSEQ_INJECT_ASM(3)
|
||||
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]")
|
||||
RSEQ_INJECT_ASM(4)
|
||||
#ifdef RSEQ_COMPARE_TWICE
|
||||
RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]")
|
||||
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]")
|
||||
#endif
|
||||
RSEQ_ASM_OP_STORE(v2, newv2)
|
||||
RSEQ_INJECT_ASM(5)
|
||||
#ifdef RSEQ_TEMPLATE_MO_RELEASE
|
||||
RSEQ_ASM_OP_FINAL_STORE_RELEASE(v, newv, 3)
|
||||
#else
|
||||
RSEQ_ASM_OP_FINAL_STORE(v, newv, 3)
|
||||
#endif
|
||||
RSEQ_INJECT_ASM(6)
|
||||
RSEQ_ASM_DEFINE_ABORT(4, abort)
|
||||
: /* gcc asm goto does not allow outputs */
|
||||
: [cpu_id] "r" (cpu),
|
||||
[current_cpu_id] "m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD),
|
||||
[rseq_cs] "m" (rseq_get_abi()->rseq_cs.arch.ptr),
|
||||
[expect] "r" (expect),
|
||||
[v] "m" (*v),
|
||||
[newv] "r" (newv),
|
||||
[v2] "m" (*v2),
|
||||
[newv2] "r" (newv2)
|
||||
RSEQ_INJECT_INPUT
|
||||
: "memory", RSEQ_ASM_TMP_REG_1
|
||||
RSEQ_INJECT_CLOBBER
|
||||
: abort, cmpfail
|
||||
#ifdef RSEQ_COMPARE_TWICE
|
||||
, error1, error2
|
||||
#endif
|
||||
);
|
||||
|
||||
return 0;
|
||||
abort:
|
||||
RSEQ_INJECT_FAILED
|
||||
return -1;
|
||||
cmpfail:
|
||||
return 1;
|
||||
#ifdef RSEQ_COMPARE_TWICE
|
||||
error1:
|
||||
rseq_bug("cpu_id comparison failed");
|
||||
error2:
|
||||
rseq_bug("expected value comparison failed");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline __always_inline
|
||||
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trymemcpy_storev)(intptr_t *v, intptr_t expect,
|
||||
void *dst, void *src, size_t len,
|
||||
intptr_t newv, int cpu)
|
||||
{
|
||||
RSEQ_INJECT_C(9)
|
||||
__asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f)
|
||||
RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[cmpfail]")
|
||||
#ifdef RSEQ_COMPARE_TWICE
|
||||
RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]")
|
||||
RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error2]")
|
||||
#endif
|
||||
RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs)
|
||||
RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f)
|
||||
RSEQ_INJECT_ASM(3)
|
||||
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]")
|
||||
RSEQ_INJECT_ASM(4)
|
||||
#ifdef RSEQ_COMPARE_TWICE
|
||||
RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]")
|
||||
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]")
|
||||
#endif
|
||||
RSEQ_ASM_OP_R_BAD_MEMCPY(dst, src, len)
|
||||
RSEQ_INJECT_ASM(5)
|
||||
#ifdef RSEQ_TEMPLATE_MO_RELEASE
|
||||
RSEQ_ASM_OP_FINAL_STORE_RELEASE(v, newv, 3)
|
||||
#else
|
||||
RSEQ_ASM_OP_FINAL_STORE(v, newv, 3)
|
||||
#endif
|
||||
RSEQ_INJECT_ASM(6)
|
||||
RSEQ_ASM_DEFINE_ABORT(4, abort)
|
||||
: /* gcc asm goto does not allow outputs */
|
||||
: [cpu_id] "r" (cpu),
|
||||
[current_cpu_id] "m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD),
|
||||
[rseq_cs] "m" (rseq_get_abi()->rseq_cs.arch.ptr),
|
||||
[expect] "r" (expect),
|
||||
[v] "m" (*v),
|
||||
[newv] "r" (newv),
|
||||
[dst] "r" (dst),
|
||||
[src] "r" (src),
|
||||
[len] "r" (len)
|
||||
RSEQ_INJECT_INPUT
|
||||
: "memory", RSEQ_ASM_TMP_REG_1, RSEQ_ASM_TMP_REG_2,
|
||||
RSEQ_ASM_TMP_REG_3, RSEQ_ASM_TMP_REG_4
|
||||
RSEQ_INJECT_CLOBBER
|
||||
: abort, cmpfail
|
||||
#ifdef RSEQ_COMPARE_TWICE
|
||||
, error1, error2
|
||||
#endif
|
||||
);
|
||||
|
||||
return 0;
|
||||
abort:
|
||||
RSEQ_INJECT_FAILED
|
||||
return -1;
|
||||
cmpfail:
|
||||
return 1;
|
||||
#ifdef RSEQ_COMPARE_TWICE
|
||||
error1:
|
||||
rseq_bug("cpu_id comparison failed");
|
||||
error2:
|
||||
rseq_bug("expected value comparison failed");
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* #if (defined(RSEQ_TEMPLATE_MO_RELAXED) || defined(RSEQ_TEMPLATE_MO_RELEASE)) &&
|
||||
(defined(RSEQ_TEMPLATE_CPU_ID) || defined(RSEQ_TEMPLATE_MM_CID)) */
|
||||
|
||||
#include "rseq-bits-reset.h"
|
||||
13
tools/testing/selftests/rseq/rseq-or1k-thread-pointer.h
Normal file
13
tools/testing/selftests/rseq/rseq-or1k-thread-pointer.h
Normal file
@@ -0,0 +1,13 @@
|
||||
/* SPDX-License-Identifier: LGPL-2.1-only OR MIT */
|
||||
#ifndef _RSEQ_OR1K_THREAD_POINTER
|
||||
#define _RSEQ_OR1K_THREAD_POINTER
|
||||
|
||||
static inline void *rseq_thread_pointer(void)
|
||||
{
|
||||
void *__thread_register;
|
||||
|
||||
__asm__ ("l.or %0, r10, r0" : "=r" (__thread_register));
|
||||
return __thread_register;
|
||||
}
|
||||
|
||||
#endif
|
||||
181
tools/testing/selftests/rseq/rseq-or1k.h
Normal file
181
tools/testing/selftests/rseq/rseq-or1k.h
Normal file
@@ -0,0 +1,181 @@
|
||||
/* SPDX-License-Identifier: LGPL-2.1 OR MIT */
|
||||
|
||||
/*
|
||||
* Select the instruction "l.nop 0x35" as the RSEQ_SIG.
|
||||
*/
|
||||
#define RSEQ_SIG 0x15000035
|
||||
|
||||
#define rseq_smp_mb() __asm__ __volatile__ ("l.msync" ::: "memory")
|
||||
#define rseq_smp_rmb() rseq_smp_mb()
|
||||
#define rseq_smp_wmb() rseq_smp_mb()
|
||||
#define RSEQ_ASM_TMP_REG_1 "r31"
|
||||
#define RSEQ_ASM_TMP_REG_2 "r29"
|
||||
#define RSEQ_ASM_TMP_REG_3 "r27"
|
||||
#define RSEQ_ASM_TMP_REG_4 "r25"
|
||||
|
||||
#define rseq_smp_load_acquire(p) \
|
||||
__extension__ ({ \
|
||||
rseq_unqual_scalar_typeof(*(p)) ____p1 = RSEQ_READ_ONCE(*(p)); \
|
||||
rseq_smp_mb(); \
|
||||
____p1; \
|
||||
})
|
||||
|
||||
#define rseq_smp_acquire__after_ctrl_dep() rseq_smp_rmb()
|
||||
|
||||
#define rseq_smp_store_release(p, v) \
|
||||
do { \
|
||||
rseq_smp_mb(); \
|
||||
RSEQ_WRITE_ONCE(*(p), v); \
|
||||
} while (0)
|
||||
|
||||
#define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, start_ip, \
|
||||
post_commit_offset, abort_ip) \
|
||||
".pushsection __rseq_cs, \"aw\"\n" \
|
||||
".balign 32\n" \
|
||||
__rseq_str(label) ":\n" \
|
||||
".long " __rseq_str(version) ", " __rseq_str(flags) "\n" \
|
||||
".long 0x0, " __rseq_str(start_ip) ", " \
|
||||
"0x0, " __rseq_str(post_commit_offset) ", " \
|
||||
"0x0, " __rseq_str(abort_ip) "\n" \
|
||||
".popsection\n\t" \
|
||||
".pushsection __rseq_cs_ptr_array, \"aw\"\n" \
|
||||
".long 0x0, " __rseq_str(label) "b\n" \
|
||||
".popsection\n"
|
||||
|
||||
#define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip) \
|
||||
__RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip, \
|
||||
((post_commit_ip) - (start_ip)), abort_ip)
|
||||
|
||||
/*
|
||||
* Exit points of a rseq critical section consist of all instructions outside
|
||||
* of the critical section where a critical section can either branch to or
|
||||
* reach through the normal course of its execution. The abort IP and the
|
||||
* post-commit IP are already part of the __rseq_cs section and should not be
|
||||
* explicitly defined as additional exit points. Knowing all exit points is
|
||||
* useful to assist debuggers stepping over the critical section.
|
||||
*/
|
||||
#define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip) \
|
||||
".pushsection __rseq_exit_point_array, \"aw\"\n" \
|
||||
".long 0x0, " __rseq_str(start_ip) ", 0x0, " __rseq_str(exit_ip) "\n" \
|
||||
".popsection\n"
|
||||
|
||||
#define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \
|
||||
RSEQ_INJECT_ASM(1) \
|
||||
"l.movhi " RSEQ_ASM_TMP_REG_1 ", hi(" __rseq_str(cs_label) ")\n"\
|
||||
"l.ori " RSEQ_ASM_TMP_REG_1 ", " RSEQ_ASM_TMP_REG_1 \
|
||||
", lo(" __rseq_str(cs_label) ")\n"\
|
||||
"l.sw %[" __rseq_str(rseq_cs) "], " RSEQ_ASM_TMP_REG_1 "\n" \
|
||||
__rseq_str(label) ":\n"
|
||||
|
||||
#define RSEQ_ASM_DEFINE_ABORT(label, abort_label) \
|
||||
"l.j 222f\n" \
|
||||
" l.nop\n" \
|
||||
".balign 4\n" \
|
||||
".long " __rseq_str(RSEQ_SIG) "\n" \
|
||||
__rseq_str(label) ":\n" \
|
||||
"l.j %l[" __rseq_str(abort_label) "]\n" \
|
||||
" l.nop\n" \
|
||||
"222:\n"
|
||||
|
||||
#define RSEQ_ASM_OP_STORE(var, value) \
|
||||
"l.sw %[" __rseq_str(var) "], %[" __rseq_str(value) "]\n"
|
||||
|
||||
#define RSEQ_ASM_OP_CMPEQ(var, expect, label) \
|
||||
"l.lwz " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" \
|
||||
"l.sfne " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(expect) "]\n" \
|
||||
"l.bf " __rseq_str(label) "\n" \
|
||||
" l.nop\n"
|
||||
|
||||
#define RSEQ_ASM_OP_CMPNE(var, expect, label) \
|
||||
"l.lwz " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" \
|
||||
"l.sfeq " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(expect) "]\n" \
|
||||
"l.bf " __rseq_str(label) "\n" \
|
||||
" l.nop\n"
|
||||
|
||||
#define RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, label) \
|
||||
RSEQ_INJECT_ASM(2) \
|
||||
RSEQ_ASM_OP_CMPEQ(current_cpu_id, cpu_id, label)
|
||||
|
||||
#define RSEQ_ASM_OP_R_LOAD(var) \
|
||||
"l.lwz " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n"
|
||||
|
||||
#define RSEQ_ASM_OP_R_STORE(var) \
|
||||
"l.sw %[" __rseq_str(var) "], " RSEQ_ASM_TMP_REG_1 "\n"
|
||||
|
||||
#define RSEQ_ASM_OP_R_LOAD_OFF(offset) \
|
||||
"l.lwz " RSEQ_ASM_TMP_REG_1 ", " \
|
||||
"%[" __rseq_str(offset) "](" RSEQ_ASM_TMP_REG_1 ")\n"
|
||||
|
||||
#define RSEQ_ASM_OP_R_ADD(count) \
|
||||
"l.add " RSEQ_ASM_TMP_REG_1 ", " RSEQ_ASM_TMP_REG_1 \
|
||||
", %[" __rseq_str(count) "]\n"
|
||||
|
||||
#define RSEQ_ASM_OP_FINAL_STORE(var, value, post_commit_label) \
|
||||
RSEQ_ASM_OP_STORE(var, value) \
|
||||
__rseq_str(post_commit_label) ":\n"
|
||||
|
||||
#define RSEQ_ASM_OP_FINAL_STORE_RELEASE(var, value, post_commit_label) \
|
||||
"l.msync\n" \
|
||||
RSEQ_ASM_OP_STORE(var, value) \
|
||||
__rseq_str(post_commit_label) ":\n"
|
||||
|
||||
#define RSEQ_ASM_OP_R_FINAL_STORE(var, post_commit_label) \
|
||||
"l.sw %[" __rseq_str(var) "], " RSEQ_ASM_TMP_REG_1 "\n" \
|
||||
__rseq_str(post_commit_label) ":\n"
|
||||
|
||||
#define RSEQ_ASM_OP_R_BAD_MEMCPY(dst, src, len) \
|
||||
"l.sfeq %[" __rseq_str(len) "], r0\n" \
|
||||
"l.bf 333f\n" \
|
||||
" l.nop\n" \
|
||||
"l.ori " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(len) "], 0\n" \
|
||||
"l.ori " RSEQ_ASM_TMP_REG_2 ", %[" __rseq_str(src) "], 0\n" \
|
||||
"l.ori " RSEQ_ASM_TMP_REG_3 ", %[" __rseq_str(dst) "], 0\n" \
|
||||
"222:\n" \
|
||||
"l.lbz " RSEQ_ASM_TMP_REG_4 ", 0(" RSEQ_ASM_TMP_REG_2 ")\n" \
|
||||
"l.sb 0(" RSEQ_ASM_TMP_REG_3 "), " RSEQ_ASM_TMP_REG_4 "\n" \
|
||||
"l.addi " RSEQ_ASM_TMP_REG_1 ", " RSEQ_ASM_TMP_REG_1 ", -1\n" \
|
||||
"l.addi " RSEQ_ASM_TMP_REG_2 ", " RSEQ_ASM_TMP_REG_2 ", 1\n" \
|
||||
"l.addi " RSEQ_ASM_TMP_REG_3 ", " RSEQ_ASM_TMP_REG_3 ", 1\n" \
|
||||
"l.sfne " RSEQ_ASM_TMP_REG_1 ", r0\n" \
|
||||
"l.bf 222b\n" \
|
||||
" l.nop\n" \
|
||||
"333:\n"
|
||||
|
||||
#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, post_commit_label) \
|
||||
"l.ori " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(ptr) "], 0\n" \
|
||||
RSEQ_ASM_OP_R_ADD(off) \
|
||||
"l.lwz " RSEQ_ASM_TMP_REG_1 ", 0(" RSEQ_ASM_TMP_REG_1 ")\n" \
|
||||
RSEQ_ASM_OP_R_ADD(inc) \
|
||||
__rseq_str(post_commit_label) ":\n"
|
||||
|
||||
/* Per-cpu-id indexing. */
|
||||
|
||||
#define RSEQ_TEMPLATE_CPU_ID
|
||||
#define RSEQ_TEMPLATE_MO_RELAXED
|
||||
#include "rseq-or1k-bits.h"
|
||||
#undef RSEQ_TEMPLATE_MO_RELAXED
|
||||
|
||||
#define RSEQ_TEMPLATE_MO_RELEASE
|
||||
#include "rseq-or1k-bits.h"
|
||||
#undef RSEQ_TEMPLATE_MO_RELEASE
|
||||
#undef RSEQ_TEMPLATE_CPU_ID
|
||||
|
||||
/* Per-mm-cid indexing. */
|
||||
|
||||
#define RSEQ_TEMPLATE_MM_CID
|
||||
#define RSEQ_TEMPLATE_MO_RELAXED
|
||||
#include "rseq-or1k-bits.h"
|
||||
#undef RSEQ_TEMPLATE_MO_RELAXED
|
||||
|
||||
#define RSEQ_TEMPLATE_MO_RELEASE
|
||||
#include "rseq-or1k-bits.h"
|
||||
#undef RSEQ_TEMPLATE_MO_RELEASE
|
||||
#undef RSEQ_TEMPLATE_MM_CID
|
||||
|
||||
/* APIs which are not based on cpu ids. */
|
||||
|
||||
#define RSEQ_TEMPLATE_CPU_ID_NONE
|
||||
#define RSEQ_TEMPLATE_MO_RELAXED
|
||||
#include "rseq-or1k-bits.h"
|
||||
#undef RSEQ_TEMPLATE_MO_RELAXED
|
||||
#undef RSEQ_TEMPLATE_CPU_ID_NONE
|
||||
@@ -12,6 +12,8 @@
|
||||
#include "rseq-x86-thread-pointer.h"
|
||||
#elif defined(__PPC__)
|
||||
#include "rseq-ppc-thread-pointer.h"
|
||||
#elif defined(__or1k__)
|
||||
#include "rseq-or1k-thread-pointer.h"
|
||||
#else
|
||||
#include "rseq-generic-thread-pointer.h"
|
||||
#endif
|
||||
|
||||
@@ -129,6 +129,8 @@ static inline struct rseq_abi *rseq_get_abi(void)
|
||||
#include <rseq-s390.h>
|
||||
#elif defined(__riscv)
|
||||
#include <rseq-riscv.h>
|
||||
#elif defined(__or1k__)
|
||||
#include <rseq-or1k.h>
|
||||
#else
|
||||
#error unsupported target
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user