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Main bcm2708/bcm2709 linux port

Browse Source 
Signed-off-by: popcornmix <popcornmix@gmail.com>
Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
This commit is contained in:
popcornmix
2013-05-12 12:24:19 +01:00
parent 83fdace666
commit ffd06bc2da
62 changed files with 6436 additions and 5 deletions
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39
arch/arm/Kconfig
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@@ -314,6 +314,42 @@ choice
default ARCH_VERSATILE if !MMU
default ARCH_MULTIPLATFORM if MMU
config ARCH_BCM2708
bool "Broadcom BCM2708 family"
select CPU_V6
select ARM_AMBA
select HAVE_SCHED_CLOCK
select NEED_MACH_GPIO_H
select NEED_MACH_MEMORY_H
select COMMON_CLK
select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
select ARM_ERRATA_411920
select MACH_BCM2708
select VC4
select FIQ
help
This enables support for Broadcom BCM2708 boards.
config ARCH_BCM2709
bool "Broadcom BCM2709 family"
select ARCH_HAS_BARRIERS if SMP
select CPU_V7
select HAVE_SMP
select ARM_AMBA
select MIGHT_HAVE_CACHE_L2X0
select HAVE_SCHED_CLOCK
select NEED_MACH_MEMORY_H
select NEED_MACH_IO_H
select COMMON_CLK
select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
select MACH_BCM2709
select VC4
select FIQ
help
This enables support for Broadcom BCM2709 boards.
config ARCH_MULTIPLATFORM
bool "Allow multiple platforms to be selected"
depends on MMU
@@ -824,6 +860,9 @@ config ARCH_VIRT
# Kconfigs may be included either alphabetically (according to the
# plat- suffix) or along side the corresponding mach-* source.
#
source "arch/arm/mach-bcm2708/Kconfig"
source "arch/arm/mach-bcm2709/Kconfig"
source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/mach-alpine/Kconfig"

8
arch/arm/Kconfig.debug
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@@ -1196,6 +1196,14 @@ choice
options; the platform specific options are deprecated
and will be soon removed.
config DEBUG_BCM2708_UART0
bool "Broadcom BCM2708 UART0 (PL011)"
depends on MACH_BCM2708
help
Say Y here if you want the debug print routines to direct
their output to UART 0. The port must have been initialised
by the boot-loader before use.
endchoice
config DEBUG_AT91_UART

2
arch/arm/Makefile
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@@ -150,6 +150,8 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
machine-$(CONFIG_ARCH_BCM2708) += bcm2708
machine-$(CONFIG_ARCH_BCM2709) += bcm2709
machine-$(CONFIG_ARCH_ALPINE) += alpine
machine-$(CONFIG_ARCH_AT91) += at91
machine-$(CONFIG_ARCH_AXXIA) += axxia

8
arch/arm/kernel/head.S
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@@ -680,6 +680,14 @@ ARM_BE8(rev16 ip, ip)
ldrcc r7, [r4], #4 @ use branch for delay slot
bcc 1b
ret lr
nop
nop
nop
nop
nop
nop
nop
nop
#endif
ENDPROC(__fixup_a_pv_table)

10
arch/arm/kernel/process.c
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@@ -98,6 +98,16 @@ void arch_cpu_idle_dead(void)
}
#endif
char bcm2708_reboot_mode = 'h';
int __init reboot_setup(char *str)
{
bcm2708_reboot_mode = str[0];
return 1;
}
__setup("reboot=", reboot_setup);
void __show_regs(struct pt_regs *regs)
{
unsigned long flags;

30
arch/arm/mach-bcm2708/Kconfig Normal file
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@@ -0,0 +1,30 @@
menu "Broadcom BCM2708 Implementations"
depends on ARCH_BCM2708
config MACH_BCM2708
bool "Broadcom BCM2708 Development Platform"
select NEED_MACH_MEMORY_H
select NEED_MACH_IO_H
select CPU_V6
help
Include support for the Broadcom(R) BCM2708 platform.
config BCM2708_DT
bool "BCM2708 Device Tree support"
depends on MACH_BCM2708
default n
select USE_OF
select ARCH_REQUIRE_GPIOLIB
select PINCTRL
select PINCTRL_BCM2835
help
Enable Device Tree support for BCM2708
config BCM2708_NOL2CACHE
bool "Videocore L2 cache disable"
depends on MACH_BCM2708
default n
help
Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
endmenu

5
arch/arm/mach-bcm2708/Makefile Normal file
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@@ -0,0 +1,5 @@
#
# Makefile for the linux kernel.
#
obj-$(CONFIG_MACH_BCM2708) += bcm2708.o armctrl.o

3
arch/arm/mach-bcm2708/Makefile.boot Normal file
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@@ -0,0 +1,3 @@
zreladdr-y := 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000

304
arch/arm/mach-bcm2708/armctrl.c Normal file
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@@ -0,0 +1,304 @@
/*
* linux/arch/arm/mach-bcm2708/armctrl.c
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/list.h>
#include <linux/io.h>
#include <linux/version.h>
#include <linux/syscore_ops.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include "armctrl.h"
/* For support of kernels >= 3.0 assume only one VIC for now*/
static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
INTERRUPT_VC_JPEG,
INTERRUPT_VC_USB,
INTERRUPT_VC_3D,
INTERRUPT_VC_DMA2,
INTERRUPT_VC_DMA3,
INTERRUPT_VC_I2C,
INTERRUPT_VC_SPI,
INTERRUPT_VC_I2SPCM,
INTERRUPT_VC_SDIO,
INTERRUPT_VC_UART,
INTERRUPT_VC_ARASANSDIO
};
static void armctrl_mask_irq(struct irq_data *d)
{
static const unsigned int disables[4] = {
ARM_IRQ_DIBL1,
ARM_IRQ_DIBL2,
ARM_IRQ_DIBL3,
0
};
unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
}
static void armctrl_unmask_irq(struct irq_data *d)
{
static const unsigned int enables[4] = {
ARM_IRQ_ENBL1,
ARM_IRQ_ENBL2,
ARM_IRQ_ENBL3,
0
};
unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
}
#ifdef CONFIG_OF
#define NR_IRQS_BANK0 21
#define NR_BANKS 3
#define IRQS_PER_BANK 32
/* from drivers/irqchip/irq-bcm2835.c */
static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq, unsigned int *out_type)
{
if (WARN_ON(intsize != 2))
return -EINVAL;
if (WARN_ON(intspec[0] >= NR_BANKS))
return -EINVAL;
if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
return -EINVAL;
if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
return -EINVAL;
if (intspec[0] == 0)
*out_hwirq = ARM_IRQ0_BASE + intspec[1];
else if (intspec[0] == 1)
*out_hwirq = ARM_IRQ1_BASE + intspec[1];
else
*out_hwirq = ARM_IRQ2_BASE + intspec[1];
/* reverse remap_irqs[] */
switch (*out_hwirq) {
case INTERRUPT_VC_JPEG:
*out_hwirq = INTERRUPT_JPEG;
break;
case INTERRUPT_VC_USB:
*out_hwirq = INTERRUPT_USB;
break;
case INTERRUPT_VC_3D:
*out_hwirq = INTERRUPT_3D;
break;
case INTERRUPT_VC_DMA2:
*out_hwirq = INTERRUPT_DMA2;
break;
case INTERRUPT_VC_DMA3:
*out_hwirq = INTERRUPT_DMA3;
break;
case INTERRUPT_VC_I2C:
*out_hwirq = INTERRUPT_I2C;
break;
case INTERRUPT_VC_SPI:
*out_hwirq = INTERRUPT_SPI;
break;
case INTERRUPT_VC_I2SPCM:
*out_hwirq = INTERRUPT_I2SPCM;
break;
case INTERRUPT_VC_SDIO:
*out_hwirq = INTERRUPT_SDIO;
break;
case INTERRUPT_VC_UART:
*out_hwirq = INTERRUPT_UART;
break;
case INTERRUPT_VC_ARASANSDIO:
*out_hwirq = INTERRUPT_ARASANSDIO;
break;
}
*out_type = IRQ_TYPE_NONE;
return 0;
}
static struct irq_domain_ops armctrl_ops = {
.xlate = armctrl_xlate
};
void __init armctrl_dt_init(void)
{
struct device_node *np;
struct irq_domain *domain;
np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic");
if (!np)
return;
domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS,
IRQ_ARMCTRL_START, 0,
&armctrl_ops, NULL);
WARN_ON(!domain);
}
#else
void __init armctrl_dt_init(void) { }
#endif /* CONFIG_OF */
#if defined(CONFIG_PM)
/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
/* Static defines
* struct armctrl_device - VIC PM device (< 3.xx)
* @sysdev: The system device which is registered. (< 3.xx)
* @irq: The IRQ number for the base of the VIC.
* @base: The register base for the VIC.
* @resume_sources: A bitmask of interrupts for resume.
* @resume_irqs: The IRQs enabled for resume.
* @int_select: Save for VIC_INT_SELECT.
* @int_enable: Save for VIC_INT_ENABLE.
* @soft_int: Save for VIC_INT_SOFT.
* @protect: Save for VIC_PROTECT.
*/
struct armctrl_info {
void __iomem *base;
int irq;
u32 resume_sources;
u32 resume_irqs;
u32 int_select;
u32 int_enable;
u32 soft_int;
u32 protect;
} armctrl;
static int armctrl_suspend(void)
{
return 0;
}
static void armctrl_resume(void)
{
return;
}
/**
* armctrl_pm_register - Register a VIC for later power management control
* @base: The base address of the VIC.
* @irq: The base IRQ for the VIC.
* @resume_sources: bitmask of interrupts allowed for resume sources.
*
* For older kernels (< 3.xx) do -
* Register the VIC with the system device tree so that it can be notified
* of suspend and resume requests and ensure that the correct actions are
* taken to re-instate the settings on resume.
*/
static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
u32 resume_sources)
{
armctrl.base = base;
armctrl.resume_sources = resume_sources;
armctrl.irq = irq;
}
static int armctrl_set_wake(struct irq_data *d, unsigned int on)
{
unsigned int off = d->irq & 31;
u32 bit = 1 << off;
if (!(bit & armctrl.resume_sources))
return -EINVAL;
if (on)
armctrl.resume_irqs |= bit;
else
armctrl.resume_irqs &= ~bit;
return 0;
}
#else
static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
u32 arg1)
{
}
#define armctrl_suspend NULL
#define armctrl_resume NULL
#define armctrl_set_wake NULL
#endif /* CONFIG_PM */
static struct syscore_ops armctrl_syscore_ops = {
.suspend = armctrl_suspend,
.resume = armctrl_resume,
};
/**
* armctrl_syscore_init - initicall to register VIC pm functions
*
* This is called via late_initcall() to register
* the resources for the VICs due to the early
* nature of the VIC's registration.
*/
static int __init armctrl_syscore_init(void)
{
register_syscore_ops(&armctrl_syscore_ops);
return 0;
}
late_initcall(armctrl_syscore_init);
static struct irq_chip armctrl_chip = {
.name = "ARMCTRL",
.irq_ack = NULL,
.irq_mask = armctrl_mask_irq,
.irq_unmask = armctrl_unmask_irq,
.irq_set_wake = armctrl_set_wake,
};
/**
* armctrl_init - initialise a vectored interrupt controller
* @base: iomem base address
* @irq_start: starting interrupt number, must be muliple of 32
* @armctrl_sources: bitmask of interrupt sources to allow
* @resume_sources: bitmask of interrupt sources to allow for resume
*/
int __init armctrl_init(void __iomem * base, unsigned int irq_start,
u32 armctrl_sources, u32 resume_sources)
{
unsigned int irq;
for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) {
unsigned int data = irq;
if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
data = remap_irqs[irq - INTERRUPT_JPEG];
irq_set_chip(irq, &armctrl_chip);
irq_set_chip_data(irq, (void *)data);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
armctrl_pm_register(base, irq_start, resume_sources);
armctrl_dt_init();
return 0;
}

27
arch/arm/mach-bcm2708/armctrl.h Normal file
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@@ -0,0 +1,27 @@
/*
* linux/arch/arm/mach-bcm2708/armctrl.h
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __BCM2708_ARMCTRL_H
#define __BCM2708_ARMCTRL_H
extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
u32 armctrl_sources, u32 resume_sources);
#endif

622
arch/arm/mach-bcm2708/bcm2708.c Normal file
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@@ -0,0 +1,622 @@
/*
* linux/arch/arm/mach-bcm2708/bcm2708.c
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/serial_8250.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <linux/interrupt.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/clockchips.h>
#include <linux/cnt32_to_63.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/gpio/machine.h>
#include <linux/version.h>
#include <linux/clkdev.h>
#include <asm/system_info.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <linux/leds.h>
#include <asm/mach-types.h>
#include <linux/sched_clock.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/timex.h>
#include <mach/system.h>
#include <linux/delay.h>
#include "bcm2708.h"
#include "armctrl.h"
#ifdef CONFIG_BCM_VC_CMA
#include <linux/broadcom/vc_cma.h>
#endif
/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
* give us IO access only to 64Mbytes of physical memory (26 bits). We could
* represent this window by setting our dmamasks to 26 bits but, in fact
* we're not going to use addresses outside this range (they're not in real
* memory) so we don't bother.
*
* In the future we might include code to use this IOMMU to remap other
* physical addresses onto VideoCore memory then the use of 32-bits would be
* more legitimate.
*/
#define DMA_MASK_BITS_COMMON 32
/* command line parameters */
static unsigned boardrev, serial;
static unsigned uart_clock = UART0_CLOCK;
static unsigned disk_led_gpio = 16;
static unsigned disk_led_active_low = 1;
static unsigned reboot_part = 0;
static unsigned use_dt = 0;
static void __init bcm2708_init_led(void);
void __init bcm2708_init_irq(void)
{
armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
}
static struct map_desc bcm2708_io_desc[] __initdata = {
{
.virtual = IO_ADDRESS(ARMCTRL_BASE),
.pfn = __phys_to_pfn(ARMCTRL_BASE),
.length = SZ_4K,
.type = MT_DEVICE},
{
.virtual = IO_ADDRESS(UART0_BASE),
.pfn = __phys_to_pfn(UART0_BASE),
.length = SZ_4K,
.type = MT_DEVICE},
{
.virtual = IO_ADDRESS(UART1_BASE),
.pfn = __phys_to_pfn(UART1_BASE),
.length = SZ_4K,
.type = MT_DEVICE},
{
.virtual = IO_ADDRESS(DMA_BASE),
.pfn = __phys_to_pfn(DMA_BASE),
.length = SZ_4K,
.type = MT_DEVICE},
{
.virtual = IO_ADDRESS(MCORE_BASE),
.pfn = __phys_to_pfn(MCORE_BASE),
.length = SZ_4K,
.type = MT_DEVICE},
{
.virtual = IO_ADDRESS(ST_BASE),
.pfn = __phys_to_pfn(ST_BASE),
.length = SZ_4K,
.type = MT_DEVICE},
{
.virtual = IO_ADDRESS(USB_BASE),
.pfn = __phys_to_pfn(USB_BASE),
.length = SZ_128K,
.type = MT_DEVICE},
{
.virtual = IO_ADDRESS(PM_BASE),
.pfn = __phys_to_pfn(PM_BASE),
.length = SZ_4K,
.type = MT_DEVICE},
{
.virtual = IO_ADDRESS(GPIO_BASE),
.pfn = __phys_to_pfn(GPIO_BASE),
.length = SZ_4K,
.type = MT_DEVICE}
};
void __init bcm2708_map_io(void)
{
iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc));
}
/* The STC is a free running counter that increments at the rate of 1MHz */
#define STC_FREQ_HZ 1000000
static inline uint32_t timer_read(void)
{
/* STC: a free running counter that increments at the rate of 1MHz */
return readl(__io_address(ST_BASE + 0x04));
}
static unsigned long bcm2708_read_current_timer(void)
{
return timer_read();
}
static u64 notrace bcm2708_read_sched_clock(void)
{
return timer_read();
}
static cycle_t clksrc_read(struct clocksource *cs)
{
return timer_read();
}
static struct clocksource clocksource_stc = {
.name = "stc",
.rating = 300,
.read = clksrc_read,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
unsigned long frc_clock_ticks32(void)
{
return timer_read();
}
static void __init bcm2708_clocksource_init(void)
{
if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
printk(KERN_ERR "timer: failed to initialize clock "
"source %s\n", clocksource_stc.name);
}
}
struct clk __init *bcm2708_clk_register(const char *name, unsigned long fixed_rate)
{
struct clk *clk;
clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT,
fixed_rate);
if (IS_ERR(clk))
pr_err("%s not registered\n", name);
return clk;
}
void __init bcm2708_register_clkdev(struct clk *clk, const char *name)
{
int ret;
ret = clk_register_clkdev(clk, NULL, name);
if (ret)
pr_err("%s alias not registered\n", name);
}
void __init bcm2708_init_clocks(void)
{
struct clk *clk;
clk = bcm2708_clk_register("uart0_clk", uart_clock);
bcm2708_register_clkdev(clk, "dev:f1");
clk = bcm2708_clk_register("sdhost_clk", 250000000);
bcm2708_register_clkdev(clk, "mmc-bcm2835.0");
bcm2708_register_clkdev(clk, "bcm2708_spi.0");
bcm2708_register_clkdev(clk, "bcm2708_i2c.0");
bcm2708_register_clkdev(clk, "bcm2708_i2c.1");
}
#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ }
#define UART0_DMA { 15, 14 }
AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
static struct amba_device *amba_devs[] __initdata = {
&uart0_device,
};
static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
static struct platform_device bcm2708_fb_device = {
.name = "bcm2708_fb",
.id = -1, /* only one bcm2708_fb */
.resource = NULL,
.num_resources = 0,
.dev = {
.dma_mask = &fb_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
},
};
static struct resource bcm2708_usb_resources[] = {
[0] = {
.start = USB_BASE,
.end = USB_BASE + SZ_128K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_USB,
.end = IRQ_USB,
.flags = IORESOURCE_IRQ,
},
};
static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
static struct platform_device bcm2708_usb_device = {
.name = "bcm2708_usb",
.id = -1, /* only one bcm2708_usb */
.resource = bcm2708_usb_resources,
.num_resources = ARRAY_SIZE(bcm2708_usb_resources),
.dev = {
.dma_mask = &usb_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
},
};
static struct resource bcm2708_vcio_resources[] = {
{
.start = ARMCTRL_0_MAIL0_BASE,
.end = ARMCTRL_0_MAIL0_BASE + SZ_64 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_ARM_MAILBOX,
.end = IRQ_ARM_MAILBOX,
.flags = IORESOURCE_IRQ,
},
};
static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
static struct platform_device bcm2708_vcio_device = {
.name = "bcm2708_vcio",
.id = -1, /* only one VideoCore I/O area */
.resource = bcm2708_vcio_resources,
.num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
.dev = {
.dma_mask = &vcio_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
},
};
int __init bcm_register_device(struct platform_device *pdev)
{
int ret;
ret = platform_device_register(pdev);
if (ret)
pr_debug("Unable to register platform device '%s': %d\n",
pdev->name, ret);
return ret;
}
/*
* Use these macros for platform and i2c devices that are present in the
* Device Tree. This way the devices are only added on non-DT systems.
*/
#define bcm_register_device_dt(pdev) \
if (!use_dt) bcm_register_device(pdev)
#define i2c_register_board_info_dt(busnum, info, n) \
if (!use_dt) i2c_register_board_info(busnum, info, n)
int calc_rsts(int partition)
{
return PM_PASSWORD |
((partition & (1 << 0)) << 0) |
((partition & (1 << 1)) << 1) |
((partition & (1 << 2)) << 2) |
((partition & (1 << 3)) << 3) |
((partition & (1 << 4)) << 4) |
((partition & (1 << 5)) << 5);
}
static void bcm2708_restart(enum reboot_mode mode, const char *cmd)
{
extern char bcm2708_reboot_mode;
uint32_t pm_rstc, pm_wdog;
uint32_t timeout = 10;
uint32_t pm_rsts = 0;
if(bcm2708_reboot_mode == 'q')
{
// NOOBS < 1.3 booting with reboot=q
pm_rsts = readl(__io_address(PM_RSTS));
pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
}
else if(bcm2708_reboot_mode == 'p')
{
// NOOBS < 1.3 halting
pm_rsts = readl(__io_address(PM_RSTS));
pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
}
else
{
pm_rsts = calc_rsts(reboot_part);
}
writel(pm_rsts, __io_address(PM_RSTS));
/* Setup watchdog for reset */
pm_rstc = readl(__io_address(PM_RSTC));
pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
writel(pm_wdog, __io_address(PM_WDOG));
writel(pm_rstc, __io_address(PM_RSTC));
}
/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
static void bcm2708_power_off(void)
{
extern char bcm2708_reboot_mode;
if(bcm2708_reboot_mode == 'q')
{
// NOOBS < v1.3
bcm2708_restart('p', "");
}
else
{
/* partition 63 is special code for HALT the bootloader knows not to boot*/
reboot_part = 63;
/* continue with normal reset mechanism */
bcm2708_restart(0, "");
}
}
static void __init bcm2708_init_uart1(void)
{
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart");
if (of_device_is_available(np)) {
pr_info("bcm2708: Mini UART enabled\n");
writel(1, __io_address(UART1_BASE + 0x4));
}
}
#ifdef CONFIG_OF
static void __init bcm2708_dt_init(void)
{
int ret;
of_clk_init(NULL);
ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
if (ret) {
pr_err("of_platform_populate failed: %d\n", ret);
/* Proceed as if CONFIG_OF was not defined */
} else {
use_dt = 1;
}
}
#else
static void __init bcm2708_dt_init(void) { }
#endif /* CONFIG_OF */
void __init bcm2708_init(void)
{
int i;
#if defined(CONFIG_BCM_VC_CMA)
vc_cma_early_init();
#endif
printk("bcm2708.uart_clock = %d\n", uart_clock);
pm_power_off = bcm2708_power_off;
bcm2708_init_clocks();
bcm2708_dt_init();
bcm_register_device(&bcm2708_vcio_device);
#ifdef CONFIG_BCM2708_GPIO
bcm_register_device_dt(&bcm2708_gpio_device);
#endif
bcm_register_device_dt(&bcm2708_fb_device);
bcm_register_device_dt(&bcm2708_usb_device);
bcm2708_init_led();
bcm2708_init_uart1();
if (!use_dt) {
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
amba_device_register(d, &iomem_resource);
}
}
system_rev = boardrev;
system_serial_low = serial;
}
static void timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *clk)
{
switch (mode) {
case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
case CLOCK_EVT_MODE_SHUTDOWN:
break;
case CLOCK_EVT_MODE_PERIODIC:
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_RESUME:
default:
printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
(int)mode);
break;
}
}
static int timer_set_next_event(unsigned long cycles,
struct clock_event_device *unused)
{
unsigned long stc;
do {
stc = readl(__io_address(ST_BASE + 0x04));
/* We could take a FIQ here, which may push ST above STC3 */
writel(stc + cycles, __io_address(ST_BASE + 0x18));
} while ((signed long) cycles >= 0 &&
(signed long) (readl(__io_address(ST_BASE + 0x04)) - stc)
>= (signed long) cycles);
return 0;
}
static struct clock_event_device timer0_clockevent = {
.name = "timer0",
.shift = 32,
.features = CLOCK_EVT_FEAT_ONESHOT,
.set_mode = timer_set_mode,
.set_next_event = timer_set_next_event,
};
/*
* IRQ handler for the timer
*/
static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = &timer0_clockevent;
writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction bcm2708_timer_irq = {
.name = "BCM2708 Timer Tick",
.flags = IRQF_TIMER | IRQF_IRQPOLL,
.handler = bcm2708_timer_interrupt,
};
/*
* Set up timer interrupt, and return the current time in seconds.
*/
static struct delay_timer bcm2708_delay_timer = {
.read_current_timer = bcm2708_read_current_timer,
.freq = STC_FREQ_HZ,
};
static void __init bcm2708_timer_init(void)
{
/* init high res timer */
bcm2708_clocksource_init();
/*
* Make irqs happen for the system timer
*/
setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
sched_clock_register(bcm2708_read_sched_clock, 32, STC_FREQ_HZ);
timer0_clockevent.mult =
div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
timer0_clockevent.max_delta_ns =
clockevent_delta2ns(0xffffffff, &timer0_clockevent);
timer0_clockevent.min_delta_ns =
clockevent_delta2ns(0xf, &timer0_clockevent);
timer0_clockevent.cpumask = cpumask_of(0);
clockevents_register_device(&timer0_clockevent);
register_current_timer_delay(&bcm2708_delay_timer);
}
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
#include <linux/leds.h>
static struct gpio_led bcm2708_leds[] = {
[0] = {
.gpio = 16,
.name = "led0",
.default_trigger = "mmc0",
.active_low = 1,
},
};
static struct gpio_led_platform_data bcm2708_led_pdata = {
.num_leds = ARRAY_SIZE(bcm2708_leds),
.leds = bcm2708_leds,
};
static struct platform_device bcm2708_led_device = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &bcm2708_led_pdata,
},
};
static void __init bcm2708_init_led(void)
{
bcm2708_leds[0].gpio = disk_led_gpio;
bcm2708_leds[0].active_low = disk_led_active_low;
bcm_register_device_dt(&bcm2708_led_device);
}
#else
static inline void bcm2708_init_led(void)
{
}
#endif
void __init bcm2708_init_early(void)
{
/*
* Some devices allocate their coherent buffers from atomic
* context. Increase size of atomic coherent pool to make sure such
* the allocations won't fail.
*/
init_dma_coherent_pool_size(SZ_4M);
}
static void __init board_reserve(void)
{
#if defined(CONFIG_BCM_VC_CMA)
vc_cma_reserve();
#endif
}
static const char * const bcm2708_compat[] = {
"brcm,bcm2708",
NULL
};
MACHINE_START(BCM2708, "BCM2708")
/* Maintainer: Broadcom Europe Ltd. */
.map_io = bcm2708_map_io,
.init_irq = bcm2708_init_irq,
.init_time = bcm2708_timer_init,
.init_machine = bcm2708_init,
.init_early = bcm2708_init_early,
.reserve = board_reserve,
.restart = bcm2708_restart,
.dt_compat = bcm2708_compat,
MACHINE_END
module_param(boardrev, uint, 0644);
module_param(serial, uint, 0644);
module_param(uart_clock, uint, 0644);
module_param(disk_led_gpio, uint, 0644);
module_param(disk_led_active_low, uint, 0644);
module_param(reboot_part, uint, 0644);

49
arch/arm/mach-bcm2708/bcm2708.h Normal file
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/*
* linux/arch/arm/mach-bcm2708/bcm2708.h
*
* BCM2708 machine support header
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __BCM2708_BCM2708_H
#define __BCM2708_BCM2708_H
#include <linux/amba/bus.h>
extern void __init bcm2708_init(void);
extern void __init bcm2708_init_irq(void);
extern void __init bcm2708_map_io(void);
extern struct sys_timer bcm2708_timer;
extern unsigned int mmc_status(struct device *dev);
#define AMBA_DEVICE(name, busid, base, plat) \
static struct amba_device name##_device = { \
.dev = { \
.coherent_dma_mask = ~0, \
.init_name = busid, \
.platform_data = plat, \
}, \
.res = { \
.start = base##_BASE, \
.end = (base##_BASE) + SZ_4K - 1,\
.flags = IORESOURCE_MEM, \
}, \
.irq = base##_IRQ, \
}
#endif

419
arch/arm/mach-bcm2708/include/mach/arm_control.h Normal file
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@@ -0,0 +1,419 @@
/*
* linux/arch/arm/mach-bcm2708/arm_control.h
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __BCM2708_ARM_CONTROL_H
#define __BCM2708_ARM_CONTROL_H
/*
* Definitions and addresses for the ARM CONTROL logic
* This file is manually generated.
*/
#define ARM_BASE 0x7E00B000
/* Basic configuration */
#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000)
#define ARM_C0_SIZ128M 0x00000000
#define ARM_C0_SIZ256M 0x00000001
#define ARM_C0_SIZ512M 0x00000002
#define ARM_C0_SIZ1G 0x00000003
#define ARM_C0_BRESP0 0x00000000
#define ARM_C0_BRESP1 0x00000004
#define ARM_C0_BRESP2 0x00000008
#define ARM_C0_BOOTHI 0x00000010
#define ARM_C0_UNUSED05 0x00000020 /* free */
#define ARM_C0_FULLPERI 0x00000040
#define ARM_C0_UNUSED78 0x00000180 /* free */
#define ARM_C0_JTAGMASK 0x00000E00
#define ARM_C0_JTAGOFF 0x00000000
#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */
#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */
#define ARM_C0_APROTMSK 0x0000F000
#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */
#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */
#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */
#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */
#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */
#define ARM_C0_PRIO_L2 0x0F000000
#define ARM_C0_PRIO_UC 0xF0000000
#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */
#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */
#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */
#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440)
#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */
#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */
#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */
#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */
#define ARM_C1_PERSON 0x00000100 /* peripherals on */
#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */
#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444)
#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */
#define ARM_S_READPEND 0x000003FF /* pending reads counter */
#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */
#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448)
#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */
#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */
#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */
#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */
#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */
#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */
#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C)
#define ARM_IDVAL 0x364D5241
/* Translation memory */
#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
/* 32 locations: 0x100.. 0x17F */
/* 32 spare means we CAN go to 64 pages.... */
/* Interrupts */
#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */
#define ARM_I0_TIMER 0x00000001 /* timer IRQ */
#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */
#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */
#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */
#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */
#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */
#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
/* todo: all I1_interrupt sources */
#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
/* todo: all I2_interrupt sources */
#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
#define ARM_IF_INDEX 0x0000007F /* FIQ select */
#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */
#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */
#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */
#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */
#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */
#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */
#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */
#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */
#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */
#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */
#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */
#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */
#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */
#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */
#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */
#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */
/* Timer */
/* For reg. fields see sp804 spec. */
#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400)
#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404)
#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410)
#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414)
#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418)
#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c)
#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
#define TIMER_CTRL_ONESHOT (1 << 0)
#define TIMER_CTRL_32BIT (1 << 1)
#define TIMER_CTRL_DIV1 (0 << 2)
#define TIMER_CTRL_DIV16 (1 << 2)
#define TIMER_CTRL_DIV256 (2 << 2)
#define TIMER_CTRL_IE (1 << 5)
#define TIMER_CTRL_PERIODIC (1 << 6)
#define TIMER_CTRL_ENABLE (1 << 7)
#define TIMER_CTRL_DBGHALT (1 << 8)
#define TIMER_CTRL_ENAFREE (1 << 9)
#define TIMER_CTRL_FREEDIV_SHIFT 16)
#define TIMER_CTRL_FREEDIV_MASK 0xff
/* Semaphores, Doorbells, Mailboxes */
#define ARM_SBM_OWN0 (ARM_BASE+0x800)
#define ARM_SBM_OWN1 (ARM_BASE+0x900)
#define ARM_SBM_OWN2 (ARM_BASE+0xA00)
#define ARM_SBM_OWN3 (ARM_BASE+0xB00)
/* MAILBOXES
* Register flags are common across all
* owner registers. See end of this section
*
* Semaphores, Doorbells, Mailboxes Owner 0
*
*/
#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
/* MAILBOX 0 access in Owner 0 area */
/* Some addresses should ONLY be used by owner 0 */
#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */
#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */
#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */
#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */
#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */
#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */
/* MAILBOX 1 access in Owner 0 area */
/* Owner 0 should only WRITE to this mailbox */
#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */
/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */
/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
/* General SEM, BELL, MAIL config/status */
#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */
#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */
#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */
#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */
/* Semaphores, Doorbells, Mailboxes Owner 1 */
#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
/* MAILBOX 0 access in Owner 0 area */
/* Owner 1 should only WRITE to this mailbox */
#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */
/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */
/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
/* MAILBOX 1 access in Owner 0 area */
#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */
#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */
#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */
#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */
#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */
#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
/* General SEM, BELL, MAIL config/status */
#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */
#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */
#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */
#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */
/* Semaphores, Doorbells, Mailboxes Owner 2 */
#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
/* MAILBOX 0 access in Owner 2 area */
/* Owner 2 should only WRITE to this mailbox */
#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */
/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */
#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */
/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */
/* MAILBOX 1 access in Owner 2 area */
/* Owner 2 should only WRITE to this mailbox */
#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */
/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */
/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
/* General SEM, BELL, MAIL config/status */
#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */
#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */
#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */
#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */
/* Semaphores, Doorbells, Mailboxes Owner 3 */
#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
/* MAILBOX 0 access in Owner 3 area */
/* Owner 3 should only WRITE to this mailbox */
#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */
/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */
#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */
/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */
/* MAILBOX 1 access in Owner 3 area */
/* Owner 3 should only WRITE to this mailbox */
#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */
/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */
/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
/* General SEM, BELL, MAIL config/status */
#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */
#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */
#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */
#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */
/* Mailbox flags. Valid for all owners */
/* Mailbox status register (...0x98) */
#define ARM_MS_FULL 0x80000000
#define ARM_MS_EMPTY 0x40000000
#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */
/* MAILBOX config/status register (...0x9C) */
/* ANY write to this register clears the error bits! */
#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */
#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */
#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */
#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */
#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */
#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
/* Bit 7 is unused */
#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */
#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
/* Semaphore clear/debug register (...0xE0) */
#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */
#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */
#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */
#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */
#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */
#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */
#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */
#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */
#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */
#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */
#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */
#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */
#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */
#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */
#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */
#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */
/* Doorbells clear/debug register (...0xE4) */
#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */
#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */
#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */
#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */
#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */
#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */
#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */
#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */
/* MY IRQS register (...0xF8) */
#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */
#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */
/* ALL IRQS register (...0xF8) */
#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */
#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */
#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */
#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */
#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */
#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */
#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */
#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */
#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */
#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */
/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
/* */
/* ARM JTAG BASH */
/* */
#define AJB_BASE 0x7e2000c0
#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
#define AJB_BITS0 0x000000
#define AJB_BITS4 0x000004
#define AJB_BITS8 0x000008
#define AJB_BITS12 0x00000C
#define AJB_BITS16 0x000010
#define AJB_BITS20 0x000014
#define AJB_BITS24 0x000018
#define AJB_BITS28 0x00001C
#define AJB_BITS32 0x000020
#define AJB_BITS34 0x000022
#define AJB_OUT_MS 0x000040
#define AJB_OUT_LS 0x000000
#define AJB_INV_CLK 0x000080
#define AJB_D0_RISE 0x000100
#define AJB_D0_FALL 0x000000
#define AJB_D1_RISE 0x000200
#define AJB_D1_FALL 0x000000
#define AJB_IN_RISE 0x000400
#define AJB_IN_FALL 0x000000
#define AJB_ENABLE 0x000800
#define AJB_HOLD0 0x000000
#define AJB_HOLD1 0x001000
#define AJB_HOLD2 0x002000
#define AJB_HOLD3 0x003000
#define AJB_RESETN 0x004000
#define AJB_CLKSHFT 16
#define AJB_BUSY 0x80000000
#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
#endif

7
arch/arm/mach-bcm2708/include/mach/clkdev.h Normal file
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#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

22
arch/arm/mach-bcm2708/include/mach/debug-macro.S Normal file
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/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 2010 Broadcom
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <mach/platform.h>
.macro addruart, rp, rv, tmp
ldr \rp, =UART0_BASE
ldr \rv, =IO_ADDRESS(UART0_BASE)
.endm
#include <debug/pl01x.S>

69
arch/arm/mach-bcm2708/include/mach/entry-macro.S Normal file
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/*
* arch/arm/mach-bcm2708/include/mach/entry-macro.S
*
* Low-level IRQ helper macros for BCM2708 platforms
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <mach/hardware.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
/* get masked status */
ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
mov \irqnr, #(ARM_IRQ0_BASE + 31)
and \tmp, \irqstat, #0x300 @ save bits 8 and 9
/* clear bits 8 and 9, and test */
bics \irqstat, \irqstat, #0x300
bne 1010f
tst \tmp, #0x100
ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
movne \irqnr, #(ARM_IRQ1_BASE + 31)
@ Mask out the interrupts also present in PEND0 - see SW-5809
bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
bicne \irqstat, #((1<<18) | (1<<19))
bne 1010f
tst \tmp, #0x200
ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
movne \irqnr, #(ARM_IRQ2_BASE + 31)
@ Mask out the interrupts also present in PEND0 - see SW-5809
bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
bicne \irqstat, #((1<<30))
beq 1020f
1010:
@ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
@ N.B. CLZ is an ARM5 instruction.
sub \tmp, \irqstat, #1
eor \irqstat, \irqstat, \tmp
clz \tmp, \irqstat
sub \irqnr, \tmp
1020: @ EQ will be set if no irqs pending
.endm

38
arch/arm/mach-bcm2708/include/mach/frc.h Normal file
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/*
* arch/arm/mach-bcm2708/include/mach/timex.h
*
* BCM2708 free running counter (timer)
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_FRC_H
#define _MACH_FRC_H
#define FRC_TICK_RATE (1000000)
/*! Free running counter incrementing at the CLOCK_TICK_RATE
(slightly faster than frc_clock_ticks63()
*/
extern unsigned long frc_clock_ticks32(void);
/*! Free running counter incrementing at the CLOCK_TICK_RATE
* Note - top bit should be ignored (see cnt32_to_63)
*/
extern unsigned long long frc_clock_ticks63(void);
#endif

28
arch/arm/mach-bcm2708/include/mach/hardware.h Normal file
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/*
* arch/arm/mach-bcm2708/include/mach/hardware.h
*
* This file contains the hardware definitions of the BCM2708 devices.
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/sizes.h>
#include <mach/platform.h>
#endif

27
arch/arm/mach-bcm2708/include/mach/io.h Normal file
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/*
* arch/arm/mach-bcm2708/include/mach/io.h
*
* Copyright (C) 2003 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) __typesafe_io(a)
#endif

196
arch/arm/mach-bcm2708/include/mach/irqs.h Normal file
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/*
* arch/arm/mach-bcm2708/include/mach/irqs.h
*
* Copyright (C) 2010 Broadcom
* Copyright (C) 2003 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _BCM2708_IRQS_H_
#define _BCM2708_IRQS_H_
#include <mach/platform.h>
/*
* IRQ interrupts definitions are the same as the INT definitions
* held within platform.h
*/
#define IRQ_ARMCTRL_START 0
#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP)
#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB)
#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D)
#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX)
#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM)
#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC)
#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE)
#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR)
#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI)
#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C)
#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI)
#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART)
#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC)
#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG)
#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG)
#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
/*
* FIQ interrupts definitions are the same as the INT definitions.
*/
#define FIQ_TIMER0 INT_TIMER0
#define FIQ_TIMER1 INT_TIMER1
#define FIQ_TIMER2 INT_TIMER2
#define FIQ_TIMER3 INT_TIMER3
#define FIQ_CODEC0 INT_CODEC0
#define FIQ_CODEC1 INT_CODEC1
#define FIQ_CODEC2 INT_CODEC2
#define FIQ_JPEG INT_JPEG
#define FIQ_ISP INT_ISP
#define FIQ_USB INT_USB
#define FIQ_3D INT_3D
#define FIQ_TRANSPOSER INT_TRANSPOSER
#define FIQ_MULTICORESYNC0 INT_MULTICORESYNC0
#define FIQ_MULTICORESYNC1 INT_MULTICORESYNC1
#define FIQ_MULTICORESYNC2 INT_MULTICORESYNC2
#define FIQ_MULTICORESYNC3 INT_MULTICORESYNC3
#define FIQ_DMA0 INT_DMA0
#define FIQ_DMA1 INT_DMA1
#define FIQ_DMA2 INT_DMA2
#define FIQ_DMA3 INT_DMA3
#define FIQ_DMA4 INT_DMA4
#define FIQ_DMA5 INT_DMA5
#define FIQ_DMA6 INT_DMA6
#define FIQ_DMA7 INT_DMA7
#define FIQ_DMA8 INT_DMA8
#define FIQ_DMA9 INT_DMA9
#define FIQ_DMA10 INT_DMA10
#define FIQ_DMA11 INT_DMA11
#define FIQ_DMA12 INT_DMA12
#define FIQ_AUX INT_AUX
#define FIQ_ARM INT_ARM
#define FIQ_VPUDMA INT_VPUDMA
#define FIQ_HOSTPORT INT_HOSTPORT
#define FIQ_VIDEOSCALER INT_VIDEOSCALER
#define FIQ_CCP2TX INT_CCP2TX
#define FIQ_SDC INT_SDC
#define FIQ_DSI0 INT_DSI0
#define FIQ_AVE INT_AVE
#define FIQ_CAM0 INT_CAM0
#define FIQ_CAM1 INT_CAM1
#define FIQ_HDMI0 INT_HDMI0
#define FIQ_HDMI1 INT_HDMI1
#define FIQ_PIXELVALVE1 INT_PIXELVALVE1
#define FIQ_I2CSPISLV INT_I2CSPISLV
#define FIQ_DSI1 INT_DSI1
#define FIQ_PWA0 INT_PWA0
#define FIQ_PWA1 INT_PWA1
#define FIQ_CPR INT_CPR
#define FIQ_SMI INT_SMI
#define FIQ_GPIO0 INT_GPIO0
#define FIQ_GPIO1 INT_GPIO1
#define FIQ_GPIO2 INT_GPIO2
#define FIQ_GPIO3 INT_GPIO3
#define FIQ_I2C INT_I2C
#define FIQ_SPI INT_SPI
#define FIQ_I2SPCM INT_I2SPCM
#define FIQ_SDIO INT_SDIO
#define FIQ_UART INT_UART
#define FIQ_SLIMBUS INT_SLIMBUS
#define FIQ_VEC INT_VEC
#define FIQ_CPG INT_CPG
#define FIQ_RNG INT_RNG
#define FIQ_ARASANSDIO INT_ARASANSDIO
#define FIQ_AVSPMON INT_AVSPMON
#define FIQ_ARM_TIMER INT_ARM_TIMER
#define FIQ_ARM_MAILBOX INT_ARM_MAILBOX
#define FIQ_ARM_DOORBELL_0 INT_ARM_DOORBELL_0
#define FIQ_ARM_DOORBELL_1 INT_ARM_DOORBELL_1
#define FIQ_VPU0_HALTED INT_VPU0_HALTED
#define FIQ_VPU1_HALTED INT_VPU1_HALTED
#define FIQ_ILLEGAL_TYPE0 INT_ILLEGAL_TYPE0
#define FIQ_ILLEGAL_TYPE1 INT_ILLEGAL_TYPE1
#define FIQ_PENDING1 INT_PENDING1
#define FIQ_PENDING2 INT_PENDING2
#define HARD_IRQS (64 + 21)
#define GPIO_IRQ_START (HARD_IRQS)
#define GPIO_IRQS (32*5)
#define SPARE_ALLOC_IRQS 64
#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS)
#define FREE_IRQS 128
#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS)
#endif /* _BCM2708_IRQS_H_ */

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/*
* arch/arm/mach-bcm2708/include/mach/memory.h
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/* Memory overview:
[ARMcore] <--virtual addr-->
[ARMmmu] <--physical addr-->
[GERTmap] <--bus add-->
[VCperiph]
*/
/*
* Physical DRAM offset.
*/
#define BCM_PLAT_PHYS_OFFSET UL(0x00000000)
#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
#ifdef CONFIG_BCM2708_NOL2CACHE
#define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
#else
#define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
#endif
/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
* will provide the offset into this area as well as setting the bits that
* stop the L1 and L2 cache from being used
*
* WARNING: this only works because the ARM is given memory at a fixed location
* (ARMMEM_OFFSET)
*/
#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
#endif

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/*
* arch/arm/mach-bcm2708/include/mach/platform.h
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _BCM2708_PLATFORM_H
#define _BCM2708_PLATFORM_H
/* macros to get at IO space when running virtually */
#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
#define __io_address(n) IOMEM(IO_ADDRESS(n))
/*
* SDRAM
*/
#define BCM2708_SDRAM_BASE 0x00000000
/*
* Logic expansion modules
*
*/
/* ------------------------------------------------------------------------
* BCM2708 ARMCTRL Registers
* ------------------------------------------------------------------------
*/
#define HW_REGISTER_RW(addr) (addr)
#define HW_REGISTER_RO(addr) (addr)
#include "arm_control.h"
#undef ARM_BASE
/*
* Definitions and addresses for the ARM CONTROL logic
* This file is manually generated.
*/
#define BCM2708_PERI_BASE 0x20000000
#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
#define ARMCTRL_BASE (ARM_BASE + 0x000)
#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
/*
* Interrupt assignments
*/
#define ARM_IRQ1_BASE 0
#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0)
#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1)
#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2)
#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3)
#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4)
#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5)
#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6)
#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7)
#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8)
#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9)
#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10)
#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11)
#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12)
#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13)
#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14)
#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15)
#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16)
#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17)
#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18)
#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19)
#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20)
#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21)
#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22)
#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23)
#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24)
#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25)
#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26)
#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27)
#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28)
#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29)
#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30)
#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31)
#define ARM_IRQ2_BASE 32
#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0)
#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1)
#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2)
#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3)
#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4)
#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5)
#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6)
#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7)
#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8)
#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9)
#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10)
#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11)
#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12)
#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13)
#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14)
#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15)
#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16)
#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17)
#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18)
#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19)
#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20)
#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21)
#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22)
#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23)
#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24)
#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25)
#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26)
#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27)
#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28)
#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29)
#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30)
#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31)
#define ARM_IRQ0_BASE 64
#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0)
#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1)
#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2)
#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3)
#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4)
#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5)
#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6)
#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7)
#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8)
#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9)
#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10)
#define INTERRUPT_USB (ARM_IRQ0_BASE + 11)
#define INTERRUPT_3D (ARM_IRQ0_BASE + 12)
#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13)
#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14)
#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15)
#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16)
#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17)
#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18)
#define INTERRUPT_UART (ARM_IRQ0_BASE + 19)
#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20)
#define MAXIRQNUM (32 + 32 + 20)
#define MAXFIQNUM (32 + 32 + 20)
#define MAX_TIMER 2
#define MAX_PERIOD 699050
#define TICKS_PER_uSEC 1
/*
* These are useconds NOT ticks.
*
*/
#define mSEC_1 1000
#define mSEC_5 (mSEC_1 * 5)
#define mSEC_10 (mSEC_1 * 10)
#define mSEC_25 (mSEC_1 * 25)
#define SEC_1 (mSEC_1 * 1000)
/*
* Watchdog
*/
#define PM_RSTC (PM_BASE+0x1c)
#define PM_RSTS (PM_BASE+0x20)
#define PM_WDOG (PM_BASE+0x24)
#define PM_WDOG_RESET 0000000000
#define PM_PASSWORD 0x5a000000
#define PM_WDOG_TIME_SET 0x000fffff
#define PM_RSTC_WRCFG_CLR 0xffffffcf
#define PM_RSTC_WRCFG_SET 0x00000030
#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
#define PM_RSTC_RESET 0x00000102
#define PM_RSTS_HADPOR_SET 0x00001000
#define PM_RSTS_HADSRH_SET 0x00000400
#define PM_RSTS_HADSRF_SET 0x00000200
#define PM_RSTS_HADSRQ_SET 0x00000100
#define PM_RSTS_HADWRH_SET 0x00000040
#define PM_RSTS_HADWRF_SET 0x00000020
#define PM_RSTS_HADWRQ_SET 0x00000010
#define PM_RSTS_HADDRH_SET 0x00000004
#define PM_RSTS_HADDRF_SET 0x00000002
#define PM_RSTS_HADDRQ_SET 0x00000001
#define UART0_CLOCK 3000000
#endif
/* END */

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/*
* arch/arm/mach-bcm2708/include/mach/system.h
*
* Copyright (C) 2010 Broadcom
* Copyright (C) 2003 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/platform.h>
static inline void arch_idle(void)
{
/*
* This should do all the clock switching
* and wait for interrupt tricks
*/
cpu_do_idle();
}
#endif

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/*
* arch/arm/mach-bcm2708/include/mach/timex.h
*
* BCM2708 sysem clock frequency
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define CLOCK_TICK_RATE (1000000)

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/*
* arch/arm/mach-bcn2708/include/mach/uncompress.h
*
* Copyright (C) 2010 Broadcom
* Copyright (C) 2003 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/io.h>
#include <linux/amba/serial.h>
#include <mach/hardware.h>
#define UART_BAUD 115200
#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
/*
* This does not append a newline
*/
static inline void putc(int c)
{
while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
barrier();
__raw_writel(c, BCM2708_UART_DR);
}
static inline void flush(void)
{
int fr;
do {
fr = __raw_readl(BCM2708_UART_FR);
barrier();
} while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
}
static inline void arch_decomp_setup(void)
{
int temp, div, rem, frac;
temp = 16 * UART_BAUD;
div = UART0_CLOCK / temp;
rem = UART0_CLOCK % temp;
temp = (8 * rem) / UART_BAUD;
frac = (temp >> 1) + (temp & 1);
/* Make sure the UART is disabled before we start */
__raw_writel(0, BCM2708_UART_CR);
/* Set the baud rate */
__raw_writel(div, BCM2708_UART_IBRD);
__raw_writel(frac, BCM2708_UART_FBRD);
/* Set the UART to 8n1, FIFO enabled */
__raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
/* Enable the UART */
__raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
BCM2708_UART_CR);
}
/*
* nothing to do
*/
#define arch_decomp_wdog()

20
arch/arm/mach-bcm2708/include/mach/vmalloc.h Normal file
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/*
* arch/arm/mach-bcm2708/include/mach/vmalloc.h
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define VMALLOC_END (0xe8000000)

42
arch/arm/mach-bcm2709/Kconfig Normal file
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menu "Broadcom BCM2709 Implementations"
depends on ARCH_BCM2709
config MACH_BCM2709
bool "Broadcom BCM2709 Development Platform"
help
Include support for the Broadcom(R) BCM2709 platform.
config BCM2709_DT
bool "BCM2709 Device Tree support"
depends on MACH_BCM2709
default n
select USE_OF
select ARCH_REQUIRE_GPIOLIB
select PINCTRL
select PINCTRL_BCM2835
help
Enable Device Tree support for BCM2709
config BCM2708_GPIO
bool "BCM2709 gpio support"
depends on MACH_BCM2709
select ARCH_REQUIRE_GPIOLIB
default y
help
Include support for the Broadcom(R) BCM2709 gpio.
config BCM2708_NOL2CACHE
bool "Videocore L2 cache disable"
depends on MACH_BCM2709
default y
help
Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
config BCM2708_SPIDEV
bool "Bind spidev to SPI0 master"
depends on MACH_BCM2709
depends on SPI
default y
help
Binds spidev driver to the SPI0 master
endmenu

6
arch/arm/mach-bcm2709/Makefile Normal file
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#
# Makefile for the linux kernel.
#
obj-$(CONFIG_MACH_BCM2709) += bcm2709.o armctrl.o
obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o

3
arch/arm/mach-bcm2709/Makefile.boot Normal file
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zreladdr-y := 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000

361
arch/arm/mach-bcm2709/armctrl.c Normal file
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/*
* linux/arch/arm/mach-bcm2708/armctrl.c
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/list.h>
#include <linux/io.h>
#include <linux/version.h>
#include <linux/syscore_ops.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include "armctrl.h"
/* For support of kernels >= 3.0 assume only one VIC for now*/
static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
INTERRUPT_VC_JPEG,
INTERRUPT_VC_USB,
INTERRUPT_VC_3D,
INTERRUPT_VC_DMA2,
INTERRUPT_VC_DMA3,
INTERRUPT_VC_I2C,
INTERRUPT_VC_SPI,
INTERRUPT_VC_I2SPCM,
INTERRUPT_VC_SDIO,
INTERRUPT_VC_UART,
INTERRUPT_VC_ARASANSDIO
};
static void armctrl_mask_irq(struct irq_data *d)
{
static const unsigned int disables[4] = {
ARM_IRQ_DIBL1,
ARM_IRQ_DIBL2,
ARM_IRQ_DIBL3,
0
};
int i;
if (d->irq >= FIQ_START) {
writel(0, __io_address(ARM_IRQ_FAST));
} else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) {
#if 1
unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ;
for (i=0; i<4; i++) // i = raw_smp_processor_id(); //
{
unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
writel(val &~ (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
}
#endif
} else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) {
#if 0
unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0;
for (i=0; i<4; i++) {
unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
writel(val &~ (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
}
#endif
} else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) {
unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
} else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) {
writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_CLR));
} else { printk("%s: %d\n", __func__, d->irq); BUG(); }
}
static void armctrl_unmask_irq(struct irq_data *d)
{
static const unsigned int enables[4] = {
ARM_IRQ_ENBL1,
ARM_IRQ_ENBL2,
ARM_IRQ_ENBL3,
0
};
int i;
if (d->irq >= FIQ_START) {
unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START;
writel(0x80 | data, __io_address(ARM_IRQ_FAST));
} else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) {
#if 1
unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ;
for (i=0; i<4; i++) // i = raw_smp_processor_id();
{
unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
writel(val | (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
}
#endif
} else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) {
#if 0
unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0;
for (i=0; i<4; i++) {
unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
writel(val | (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
}
#endif
} else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) {
unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
} else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) {
writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_SET));
} else { printk("%s: %d\n", __func__, d->irq); BUG(); }
}
#ifdef CONFIG_OF
#define NR_IRQS_BANK0 21
#define NR_BANKS 4
#define IRQS_PER_BANK 32
/* from drivers/irqchip/irq-bcm2835.c */
static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq, unsigned int *out_type)
{
if (WARN_ON(intsize != 2))
return -EINVAL;
if (WARN_ON(intspec[0] >= NR_BANKS))
return -EINVAL;
if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
return -EINVAL;
if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
return -EINVAL;
if (WARN_ON(intspec[0] == 3 && intspec[1] > 3 && intspec[1] != 5 && intspec[1] != 9))
return -EINVAL;
if (intspec[0] == 0)
*out_hwirq = ARM_IRQ0_BASE + intspec[1];
else if (intspec[0] == 1)
*out_hwirq = ARM_IRQ1_BASE + intspec[1];
else if (intspec[0] == 2)
*out_hwirq = ARM_IRQ2_BASE + intspec[1];
else
*out_hwirq = ARM_IRQ_LOCAL_BASE + intspec[1];
/* reverse remap_irqs[] */
switch (*out_hwirq) {
case INTERRUPT_VC_JPEG:
*out_hwirq = INTERRUPT_JPEG;
break;
case INTERRUPT_VC_USB:
*out_hwirq = INTERRUPT_USB;
break;
case INTERRUPT_VC_3D:
*out_hwirq = INTERRUPT_3D;
break;
case INTERRUPT_VC_DMA2:
*out_hwirq = INTERRUPT_DMA2;
break;
case INTERRUPT_VC_DMA3:
*out_hwirq = INTERRUPT_DMA3;
break;
case INTERRUPT_VC_I2C:
*out_hwirq = INTERRUPT_I2C;
break;
case INTERRUPT_VC_SPI:
*out_hwirq = INTERRUPT_SPI;
break;
case INTERRUPT_VC_I2SPCM:
*out_hwirq = INTERRUPT_I2SPCM;
break;
case INTERRUPT_VC_SDIO:
*out_hwirq = INTERRUPT_SDIO;
break;
case INTERRUPT_VC_UART:
*out_hwirq = INTERRUPT_UART;
break;
case INTERRUPT_VC_ARASANSDIO:
*out_hwirq = INTERRUPT_ARASANSDIO;
break;
}
*out_type = IRQ_TYPE_NONE;
return 0;
}
static struct irq_domain_ops armctrl_ops = {
.xlate = armctrl_xlate
};
void __init armctrl_dt_init(void)
{
struct device_node *np;
struct irq_domain *domain;
np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic");
if (!np)
return;
domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS,
IRQ_ARMCTRL_START, 0,
&armctrl_ops, NULL);
WARN_ON(!domain);
}
#else
void __init armctrl_dt_init(void) { }
#endif /* CONFIG_OF */
#if defined(CONFIG_PM)
/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
/* Static defines
* struct armctrl_device - VIC PM device (< 3.xx)
* @sysdev: The system device which is registered. (< 3.xx)
* @irq: The IRQ number for the base of the VIC.
* @base: The register base for the VIC.
* @resume_sources: A bitmask of interrupts for resume.
* @resume_irqs: The IRQs enabled for resume.
* @int_select: Save for VIC_INT_SELECT.
* @int_enable: Save for VIC_INT_ENABLE.
* @soft_int: Save for VIC_INT_SOFT.
* @protect: Save for VIC_PROTECT.
*/
struct armctrl_info {
void __iomem *base;
int irq;
u32 resume_sources;
u32 resume_irqs;
u32 int_select;
u32 int_enable;
u32 soft_int;
u32 protect;
} armctrl;
static int armctrl_suspend(void)
{
return 0;
}
static void armctrl_resume(void)
{
return;
}
/**
* armctrl_pm_register - Register a VIC for later power management control
* @base: The base address of the VIC.
* @irq: The base IRQ for the VIC.
* @resume_sources: bitmask of interrupts allowed for resume sources.
*
* For older kernels (< 3.xx) do -
* Register the VIC with the system device tree so that it can be notified
* of suspend and resume requests and ensure that the correct actions are
* taken to re-instate the settings on resume.
*/
static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
u32 resume_sources)
{
armctrl.base = base;
armctrl.resume_sources = resume_sources;
armctrl.irq = irq;
}
static int armctrl_set_wake(struct irq_data *d, unsigned int on)
{
unsigned int off = d->irq & 31;
u32 bit = 1 << off;
if (!(bit & armctrl.resume_sources))
return -EINVAL;
if (on)
armctrl.resume_irqs |= bit;
else
armctrl.resume_irqs &= ~bit;
return 0;
}
#else
static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
u32 arg1)
{
}
#define armctrl_suspend NULL
#define armctrl_resume NULL
#define armctrl_set_wake NULL
#endif /* CONFIG_PM */
static struct syscore_ops armctrl_syscore_ops = {
.suspend = armctrl_suspend,
.resume = armctrl_resume,
};
/**
* armctrl_syscore_init - initicall to register VIC pm functions
*
* This is called via late_initcall() to register
* the resources for the VICs due to the early
* nature of the VIC's registration.
*/
static int __init armctrl_syscore_init(void)
{
register_syscore_ops(&armctrl_syscore_ops);
return 0;
}
late_initcall(armctrl_syscore_init);
static struct irq_chip armctrl_chip = {
.name = "ARMCTRL",
.irq_ack = NULL,
.irq_mask = armctrl_mask_irq,
.irq_unmask = armctrl_unmask_irq,
.irq_set_wake = armctrl_set_wake,
};
/**
* armctrl_init - initialise a vectored interrupt controller
* @base: iomem base address
* @irq_start: starting interrupt number, must be muliple of 32
* @armctrl_sources: bitmask of interrupt sources to allow
* @resume_sources: bitmask of interrupt sources to allow for resume
*/
int __init armctrl_init(void __iomem * base, unsigned int irq_start,
u32 armctrl_sources, u32 resume_sources)
{
unsigned int irq;
for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) {
unsigned int data = irq;
if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
data = remap_irqs[irq - INTERRUPT_JPEG];
if (irq >= IRQ_ARM_LOCAL_CNTPSIRQ && irq <= IRQ_ARM_LOCAL_TIMER) {
irq_set_percpu_devid(irq);
irq_set_chip_and_handler(irq, &armctrl_chip, handle_percpu_devid_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
} else {
irq_set_chip_and_handler(irq, &armctrl_chip, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
irq_set_chip_data(irq, (void *)data);
}
armctrl_pm_register(base, irq_start, resume_sources);
init_FIQ(FIQ_START);
armctrl_dt_init();
return 0;
}

27
arch/arm/mach-bcm2709/armctrl.h Normal file
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/*
* linux/arch/arm/mach-bcm2708/armctrl.h
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __BCM2708_ARMCTRL_H
#define __BCM2708_ARMCTRL_H
extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
u32 armctrl_sources, u32 resume_sources);
#endif

426
arch/arm/mach-bcm2709/bcm2708_gpio.c Normal file
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/*
* linux/arch/arm/mach-bcm2708/bcm2708_gpio.c
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/spinlock.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/list.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <mach/gpio.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <mach/platform.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_data/bcm2708.h>
#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
#define DRIVER_NAME BCM_GPIO_DRIVER_NAME
#define BCM_GPIO_USE_IRQ 1
#define GPIOFSEL(x) (0x00+(x)*4)
#define GPIOSET(x) (0x1c+(x)*4)
#define GPIOCLR(x) (0x28+(x)*4)
#define GPIOLEV(x) (0x34+(x)*4)
#define GPIOEDS(x) (0x40+(x)*4)
#define GPIOREN(x) (0x4c+(x)*4)
#define GPIOFEN(x) (0x58+(x)*4)
#define GPIOHEN(x) (0x64+(x)*4)
#define GPIOLEN(x) (0x70+(x)*4)
#define GPIOAREN(x) (0x7c+(x)*4)
#define GPIOAFEN(x) (0x88+(x)*4)
#define GPIOUD(x) (0x94+(x)*4)
#define GPIOUDCLK(x) (0x98+(x)*4)
#define GPIO_BANKS 2
enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT,
GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4,
GPIO_FSEL_ALT0, GPIO_FSEL_ALT1,
GPIO_FSEL_ALT2, GPIO_FSEL_ALT3,
};
/* Each of the two spinlocks protects a different set of hardware
* regiters and data structurs. This decouples the code of the IRQ from
* the GPIO code. This also makes the case of a GPIO routine call from
* the IRQ code simpler.
*/
static DEFINE_SPINLOCK(lock); /* GPIO registers */
struct bcm2708_gpio {
struct list_head list;
void __iomem *base;
struct gpio_chip gc;
unsigned long rising[(BCM2708_NR_GPIOS + 31) / 32];
unsigned long falling[(BCM2708_NR_GPIOS + 31) / 32];
unsigned long high[(BCM2708_NR_GPIOS + 31) / 32];
unsigned long low[(BCM2708_NR_GPIOS + 31) / 32];
};
static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset,
int function)
{
struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
unsigned long flags;
unsigned gpiodir;
unsigned gpio_bank = offset / 10;
unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function);
if (offset >= BCM2708_NR_GPIOS)
return -EINVAL;
spin_lock_irqsave(&lock, flags);
gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
gpiodir &= ~(7 << gpio_field_offset);
gpiodir |= function << gpio_field_offset;
writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank));
spin_unlock_irqrestore(&lock, flags);
gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
return 0;
}
static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset)
{
return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT);
}
static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
int value)
{
int ret;
ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT);
if (ret >= 0)
bcm2708_gpio_set(gc, offset, value);
return ret;
}
static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset)
{
struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
unsigned gpio_bank = offset / 32;
unsigned gpio_field_offset = (offset - 32 * gpio_bank);
unsigned lev;
if (offset >= BCM2708_NR_GPIOS)
return 0;
lev = readl(gpio->base + GPIOLEV(gpio_bank));
//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset));
return 0x1 & (lev >> gpio_field_offset);
}
static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
{
struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
unsigned gpio_bank = offset / 32;
unsigned gpio_field_offset = (offset - 32 * gpio_bank);
//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value);
if (offset >= BCM2708_NR_GPIOS)
return;
if (value)
writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank));
else
writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank));
}
/**********************
* extension to configure pullups
*/
int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset,
bcm2708_gpio_pull_t value)
{
struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
unsigned gpio_bank = offset / 32;
unsigned gpio_field_offset = (offset - 32 * gpio_bank);
if (offset >= BCM2708_NR_GPIOS)
return -EINVAL;
switch (value) {
case BCM2708_PULL_UP:
writel(2, gpio->base + GPIOUD(0));
break;
case BCM2708_PULL_DOWN:
writel(1, gpio->base + GPIOUD(0));
break;
case BCM2708_PULL_OFF:
writel(0, gpio->base + GPIOUD(0));
break;
}
udelay(5);
writel(1 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank));
udelay(5);
writel(0, gpio->base + GPIOUD(0));
writel(0 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank));
return 0;
}
EXPORT_SYMBOL(bcm2708_gpio_setpull);
/*************************************************************************************************************************
* bcm2708 GPIO IRQ
*/
#if BCM_GPIO_USE_IRQ
static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
{
return gpio_to_irq(gpio);
}
static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type)
{
unsigned irq = d->irq;
struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
unsigned gn = irq_to_gpio(irq);
unsigned gb = gn / 32;
unsigned go = gn % 32;
gpio->rising[gb] &= ~(1 << go);
gpio->falling[gb] &= ~(1 << go);
gpio->high[gb] &= ~(1 << go);
gpio->low[gb] &= ~(1 << go);
if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
return -EINVAL;
if (type & IRQ_TYPE_EDGE_RISING)
gpio->rising[gb] |= (1 << go);
if (type & IRQ_TYPE_EDGE_FALLING)
gpio->falling[gb] |= (1 << go);
if (type & IRQ_TYPE_LEVEL_HIGH)
gpio->high[gb] |= (1 << go);
if (type & IRQ_TYPE_LEVEL_LOW)
gpio->low[gb] |= (1 << go);
return 0;
}
static void bcm2708_gpio_irq_mask(struct irq_data *d)
{
unsigned irq = d->irq;
struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
unsigned gn = irq_to_gpio(irq);
unsigned gb = gn / 32;
unsigned long rising = readl(gpio->base + GPIOREN(gb));
unsigned long falling = readl(gpio->base + GPIOFEN(gb));
unsigned long high = readl(gpio->base + GPIOHEN(gb));
unsigned long low = readl(gpio->base + GPIOLEN(gb));
gn = gn % 32;
writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb));
writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb));
}
static void bcm2708_gpio_irq_unmask(struct irq_data *d)
{
unsigned irq = d->irq;
struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
unsigned gn = irq_to_gpio(irq);
unsigned gb = gn / 32;
unsigned go = gn % 32;
unsigned long rising = readl(gpio->base + GPIOREN(gb));
unsigned long falling = readl(gpio->base + GPIOFEN(gb));
unsigned long high = readl(gpio->base + GPIOHEN(gb));
unsigned long low = readl(gpio->base + GPIOLEN(gb));
if (gpio->rising[gb] & (1 << go)) {
writel(rising | (1 << go), gpio->base + GPIOREN(gb));
} else {
writel(rising & ~(1 << go), gpio->base + GPIOREN(gb));
}
if (gpio->falling[gb] & (1 << go)) {
writel(falling | (1 << go), gpio->base + GPIOFEN(gb));
} else {
writel(falling & ~(1 << go), gpio->base + GPIOFEN(gb));
}
if (gpio->high[gb] & (1 << go)) {
writel(high | (1 << go), gpio->base + GPIOHEN(gb));
} else {
writel(high & ~(1 << go), gpio->base + GPIOHEN(gb));
}
if (gpio->low[gb] & (1 << go)) {
writel(low | (1 << go), gpio->base + GPIOLEN(gb));
} else {
writel(low & ~(1 << go), gpio->base + GPIOLEN(gb));
}
}
static struct irq_chip bcm2708_irqchip = {
.name = "GPIO",
.irq_enable = bcm2708_gpio_irq_unmask,
.irq_disable = bcm2708_gpio_irq_mask,
.irq_unmask = bcm2708_gpio_irq_unmask,
.irq_mask = bcm2708_gpio_irq_mask,
.irq_set_type = bcm2708_gpio_irq_set_type,
};
static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id)
{
unsigned long edsr;
unsigned bank;
int i;
unsigned gpio;
unsigned level_bits;
struct bcm2708_gpio *gpio_data = dev_id;
for (bank = 0; bank < GPIO_BANKS; bank++) {
edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank));
level_bits = gpio_data->high[bank] | gpio_data->low[bank];
for_each_set_bit(i, &edsr, 32) {
gpio = i + bank * 32;
/* ack edge triggered IRQs immediately */
if (!(level_bits & (1<<i)))
writel(1<<i,
__io_address(GPIO_BASE) + GPIOEDS(bank));
generic_handle_irq(gpio_to_irq(gpio));
/* ack level triggered IRQ after handling them */
if (level_bits & (1<<i))
writel(1<<i,
__io_address(GPIO_BASE) + GPIOEDS(bank));
}
}
return IRQ_HANDLED;
}
static struct irqaction bcm2708_gpio_irq = {
.name = "BCM2708 GPIO catchall handler",
.flags = IRQF_TIMER | IRQF_IRQPOLL,
.handler = bcm2708_gpio_interrupt,
};
static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
{
unsigned irq;
ucb->gc.to_irq = bcm2708_gpio_to_irq;
for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) {
irq_set_chip_data(irq, ucb);
irq_set_chip_and_handler(irq, &bcm2708_irqchip,
handle_simple_irq);
set_irq_flags(irq, IRQF_VALID);
}
bcm2708_gpio_irq.dev_id = ucb;
setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq);
}
#else
static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
{
}
#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */
static int bcm2708_gpio_probe(struct platform_device *dev)
{
struct bcm2708_gpio *ucb;
struct resource *res;
int bank;
int err = 0;
printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev);
ucb = kzalloc(sizeof(*ucb), GFP_KERNEL);
if (NULL == ucb) {
printk(KERN_ERR DRIVER_NAME ": failed to allocate "
"mailbox memory\n");
err = -ENOMEM;
goto err;
}
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
platform_set_drvdata(dev, ucb);
ucb->base = __io_address(GPIO_BASE);
ucb->gc.label = "bcm2708_gpio";
ucb->gc.base = 0;
ucb->gc.ngpio = BCM2708_NR_GPIOS;
ucb->gc.owner = THIS_MODULE;
ucb->gc.direction_input = bcm2708_gpio_dir_in;
ucb->gc.direction_output = bcm2708_gpio_dir_out;
ucb->gc.get = bcm2708_gpio_get;
ucb->gc.set = bcm2708_gpio_set;
ucb->gc.can_sleep = 0;
for (bank = 0; bank < GPIO_BANKS; bank++) {
writel(0, ucb->base + GPIOREN(bank));
writel(0, ucb->base + GPIOFEN(bank));
writel(0, ucb->base + GPIOHEN(bank));
writel(0, ucb->base + GPIOLEN(bank));
writel(0, ucb->base + GPIOAREN(bank));
writel(0, ucb->base + GPIOAFEN(bank));
writel(~0, ucb->base + GPIOEDS(bank));
}
bcm2708_gpio_irq_init(ucb);
err = gpiochip_add(&ucb->gc);
err:
return err;
}
static int bcm2708_gpio_remove(struct platform_device *dev)
{
int err = 0;
struct bcm2708_gpio *ucb = platform_get_drvdata(dev);
printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev);
gpiochip_remove(&ucb->gc);
platform_set_drvdata(dev, NULL);
kfree(ucb);
return err;
}
static struct platform_driver bcm2708_gpio_driver = {
.probe = bcm2708_gpio_probe,
.remove = bcm2708_gpio_remove,
.driver = {
.name = "bcm2708_gpio"},
};
static int __init bcm2708_gpio_init(void)
{
return platform_driver_register(&bcm2708_gpio_driver);
}
static void __exit bcm2708_gpio_exit(void)
{
platform_driver_unregister(&bcm2708_gpio_driver);
}
module_init(bcm2708_gpio_init);
module_exit(bcm2708_gpio_exit);
MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver");
MODULE_LICENSE("GPL");

801
arch/arm/mach-bcm2709/bcm2709.c Normal file
View File

@@ -0,0 +1,801 @@
/*
* linux/arch/arm/mach-bcm2709/bcm2709.c
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/serial_8250.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <linux/interrupt.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/clockchips.h>
#include <linux/cnt32_to_63.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/gpio/machine.h>
#include <linux/version.h>
#include <linux/clkdev.h>
#include <asm/system_info.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <linux/leds.h>
#include <asm/mach-types.h>
#include <asm/cputype.h>
#include <linux/sched_clock.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/timex.h>
#include <mach/system.h>
#include <linux/delay.h>
#include "bcm2709.h"
#include "armctrl.h"
#ifdef CONFIG_BCM_VC_CMA
#include <linux/broadcom/vc_cma.h>
#endif
//#define SYSTEM_TIMER
/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
* give us IO access only to 64Mbytes of physical memory (26 bits). We could
* represent this window by setting our dmamasks to 26 bits but, in fact
* we're not going to use addresses outside this range (they're not in real
* memory) so we don't bother.
*
* In the future we might include code to use this IOMMU to remap other
* physical addresses onto VideoCore memory then the use of 32-bits would be
* more legitimate.
*/
#define DMA_MASK_BITS_COMMON 32
/* command line parameters */
static unsigned boardrev, serial;
static unsigned uart_clock = UART0_CLOCK;
static unsigned disk_led_gpio = 16;
static unsigned disk_led_active_low = 1;
static unsigned reboot_part = 0;
static unsigned use_dt = 0;
static void __init bcm2709_init_led(void);
void __init bcm2709_init_irq(void)
{
armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
}
static struct map_desc bcm2709_io_desc[] __initdata = {
{
.virtual = IO_ADDRESS(ARMCTRL_BASE),
.pfn = __phys_to_pfn(ARMCTRL_BASE),
.length = SZ_4K,
.type = MT_DEVICE},
{
.virtual = IO_ADDRESS(UART0_BASE),
.pfn = __phys_to_pfn(UART0_BASE),
.length = SZ_4K,
.type = MT_DEVICE},
{
.virtual = IO_ADDRESS(UART1_BASE),
.pfn = __phys_to_pfn(UART1_BASE),
.length = SZ_4K,
.type = MT_DEVICE},
{
.virtual = IO_ADDRESS(DMA_BASE),
.pfn = __phys_to_pfn(DMA_BASE),
.length = SZ_4K,
.type = MT_DEVICE},
{
.virtual = IO_ADDRESS(MCORE_BASE),
.pfn = __phys_to_pfn(MCORE_BASE),
.length = SZ_4K,
.type = MT_DEVICE},
{
.virtual = IO_ADDRESS(ST_BASE),
.pfn = __phys_to_pfn(ST_BASE),
.length = SZ_4K,
.type = MT_DEVICE},
{
.virtual = IO_ADDRESS(USB_BASE),
.pfn = __phys_to_pfn(USB_BASE),
.length = SZ_128K,
.type = MT_DEVICE},
{
.virtual = IO_ADDRESS(PM_BASE),
.pfn = __phys_to_pfn(PM_BASE),
.length = SZ_4K,
.type = MT_DEVICE},
{
.virtual = IO_ADDRESS(GPIO_BASE),
.pfn = __phys_to_pfn(GPIO_BASE),
.length = SZ_4K,
.type = MT_DEVICE},
{
.virtual = IO_ADDRESS(ARM_LOCAL_BASE),
.pfn = __phys_to_pfn(ARM_LOCAL_BASE),
.length = SZ_4K,
.type = MT_DEVICE},
};
void __init bcm2709_map_io(void)
{
iotable_init(bcm2709_io_desc, ARRAY_SIZE(bcm2709_io_desc));
}
#ifdef SYSTEM_TIMER
/* The STC is a free running counter that increments at the rate of 1MHz */
#define STC_FREQ_HZ 1000000
static inline uint32_t timer_read(void)
{
/* STC: a free running counter that increments at the rate of 1MHz */
return readl(__io_address(ST_BASE + 0x04));
}
static unsigned long bcm2709_read_current_timer(void)
{
return timer_read();
}
static u64 notrace bcm2709_read_sched_clock(void)
{
return timer_read();
}
static cycle_t clksrc_read(struct clocksource *cs)
{
return timer_read();
}
static struct clocksource clocksource_stc = {
.name = "stc",
.rating = 300,
.read = clksrc_read,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
unsigned long frc_clock_ticks32(void)
{
return timer_read();
}
static void __init bcm2709_clocksource_init(void)
{
if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
printk(KERN_ERR "timer: failed to initialize clock "
"source %s\n", clocksource_stc.name);
}
}
#endif
struct clk __init *bcm2709_clk_register(const char *name, unsigned long fixed_rate)
{
struct clk *clk;
clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT,
fixed_rate);
if (IS_ERR(clk))
pr_err("%s not registered\n", name);
return clk;
}
void __init bcm2709_register_clkdev(struct clk *clk, const char *name)
{
int ret;
ret = clk_register_clkdev(clk, NULL, name);
if (ret)
pr_err("%s alias not registered\n", name);
}
void __init bcm2709_init_clocks(void)
{
struct clk *clk;
clk = bcm2709_clk_register("uart0_clk", uart_clock);
bcm2709_register_clkdev(clk, "dev:f1");
clk = bcm2709_clk_register("sdhost_clk", 250000000);
bcm2709_register_clkdev(clk, "mmc-bcm2835.0");
bcm2709_register_clkdev(clk, "bcm2708_spi.0");
bcm2709_register_clkdev(clk, "bcm2708_i2c.0");
bcm2709_register_clkdev(clk, "bcm2708_i2c.1");
}
#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ }
#define UART0_DMA { 15, 14 }
AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
static struct amba_device *amba_devs[] __initdata = {
&uart0_device,
};
static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
static struct platform_device bcm2708_fb_device = {
.name = "bcm2708_fb",
.id = -1, /* only one bcm2708_fb */
.resource = NULL,
.num_resources = 0,
.dev = {
.dma_mask = &fb_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
},
};
static struct resource bcm2708_usb_resources[] = {
[0] = {
.start = USB_BASE,
.end = USB_BASE + SZ_128K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MPHI_BASE,
.end = MPHI_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = IRQ_HOSTPORT,
.end = IRQ_HOSTPORT,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = IRQ_USB,
.end = IRQ_USB,
.flags = IORESOURCE_IRQ,
},
[4] = {
.start = ARM_LOCAL_BASE,
.end = ARM_LOCAL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[5] = {
.start = IRQ_ARM_LOCAL_MAILBOX1,
.end = IRQ_ARM_LOCAL_MAILBOX1,
.flags = IORESOURCE_IRQ
},
};
static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
static struct platform_device bcm2708_usb_device = {
.name = "bcm2708_usb",
.id = -1, /* only one bcm2708_usb */
.resource = bcm2708_usb_resources,
.num_resources = ARRAY_SIZE(bcm2708_usb_resources),
.dev = {
.dma_mask = &usb_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
},
};
static struct resource bcm2708_vcio_resources[] = {
{
.start = ARMCTRL_0_MAIL0_BASE,
.end = ARMCTRL_0_MAIL0_BASE + SZ_64 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_ARM_MAILBOX,
.end = IRQ_ARM_MAILBOX,
.flags = IORESOURCE_IRQ,
},
};
static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
static struct platform_device bcm2708_vcio_device = {
.name = "bcm2708_vcio",
.id = -1, /* only one VideoCore I/O area */
.resource = bcm2708_vcio_resources,
.num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
.dev = {
.dma_mask = &vcio_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
},
};
int __init bcm_register_device(struct platform_device *pdev)
{
int ret;
ret = platform_device_register(pdev);
if (ret)
pr_debug("Unable to register platform device '%s': %d\n",
pdev->name, ret);
return ret;
}
/*
* Use these macros for platform and i2c devices that are present in the
* Device Tree. This way the devices are only added on non-DT systems.
*/
#define bcm_register_device_dt(pdev) \
if (!use_dt) bcm_register_device(pdev)
#define i2c_register_board_info_dt(busnum, info, n) \
if (!use_dt) i2c_register_board_info(busnum, info, n)
int calc_rsts(int partition)
{
return PM_PASSWORD |
((partition & (1 << 0)) << 0) |
((partition & (1 << 1)) << 1) |
((partition & (1 << 2)) << 2) |
((partition & (1 << 3)) << 3) |
((partition & (1 << 4)) << 4) |
((partition & (1 << 5)) << 5);
}
static void bcm2709_restart(enum reboot_mode mode, const char *cmd)
{
extern char bcm2708_reboot_mode;
uint32_t pm_rstc, pm_wdog;
uint32_t timeout = 10;
uint32_t pm_rsts = 0;
if(bcm2708_reboot_mode == 'q')
{
// NOOBS < 1.3 booting with reboot=q
pm_rsts = readl(__io_address(PM_RSTS));
pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
}
else if(bcm2708_reboot_mode == 'p')
{
// NOOBS < 1.3 halting
pm_rsts = readl(__io_address(PM_RSTS));
pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
}
else
{
pm_rsts = calc_rsts(reboot_part);
}
writel(pm_rsts, __io_address(PM_RSTS));
/* Setup watchdog for reset */
pm_rstc = readl(__io_address(PM_RSTC));
pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
writel(pm_wdog, __io_address(PM_WDOG));
writel(pm_rstc, __io_address(PM_RSTC));
}
/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
static void bcm2709_power_off(void)
{
extern char bcm2708_reboot_mode;
if(bcm2708_reboot_mode == 'q')
{
// NOOBS < v1.3
bcm2709_restart('p', "");
}
else
{
/* partition 63 is special code for HALT the bootloader knows not to boot*/
reboot_part = 63;
/* continue with normal reset mechanism */
bcm2709_restart(0, "");
}
}
static void __init bcm2709_init_uart1(void)
{
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart");
if (of_device_is_available(np)) {
pr_info("bcm2709: Mini UART enabled\n");
writel(1, __io_address(UART1_BASE + 0x4));
}
}
#ifdef CONFIG_OF
static void __init bcm2709_dt_init(void)
{
int ret;
of_clk_init(NULL);
ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
if (ret) {
pr_err("of_platform_populate failed: %d\n", ret);
/* Proceed as if CONFIG_OF was not defined */
} else {
use_dt = 1;
}
}
#else
static void __init bcm2709_dt_init(void) { }
#endif /* CONFIG_OF */
void __init bcm2709_init(void)
{
int i;
#if defined(CONFIG_BCM_VC_CMA)
vc_cma_early_init();
#endif
printk("bcm2709.uart_clock = %d\n", uart_clock);
pm_power_off = bcm2709_power_off;
bcm2709_init_clocks();
bcm2709_dt_init();
bcm_register_device(&bcm2708_vcio_device);
#ifdef CONFIG_BCM2708_GPIO
bcm_register_device_dt(&bcm2708_gpio_device);
#endif
bcm_register_device_dt(&bcm2708_fb_device);
bcm_register_device_dt(&bcm2708_usb_device);
bcm2708_init_led();
bcm2708_init_uart1();
if (!use_dt) {
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
amba_device_register(d, &iomem_resource);
}
}
system_rev = boardrev;
system_serial_low = serial;
}
#ifdef SYSTEM_TIMER
static void timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *clk)
{
switch (mode) {
case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
case CLOCK_EVT_MODE_SHUTDOWN:
break;
case CLOCK_EVT_MODE_PERIODIC:
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_RESUME:
default:
printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
(int)mode);
break;
}
}
static int timer_set_next_event(unsigned long cycles,
struct clock_event_device *unused)
{
unsigned long stc;
do {
stc = readl(__io_address(ST_BASE + 0x04));
/* We could take a FIQ here, which may push ST above STC3 */
writel(stc + cycles, __io_address(ST_BASE + 0x18));
} while ((signed long) cycles >= 0 &&
(signed long) (readl(__io_address(ST_BASE + 0x04)) - stc)
>= (signed long) cycles);
return 0;
}
static struct clock_event_device timer0_clockevent = {
.name = "timer0",
.shift = 32,
.features = CLOCK_EVT_FEAT_ONESHOT,
.set_mode = timer_set_mode,
.set_next_event = timer_set_next_event,
};
/*
* IRQ handler for the timer
*/
static irqreturn_t bcm2709_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = &timer0_clockevent;
writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction bcm2709_timer_irq = {
.name = "BCM2709 Timer Tick",
.flags = IRQF_TIMER | IRQF_IRQPOLL,
.handler = bcm2709_timer_interrupt,
};
/*
* Set up timer interrupt, and return the current time in seconds.
*/
static struct delay_timer bcm2709_delay_timer = {
.read_current_timer = bcm2709_read_current_timer,
.freq = STC_FREQ_HZ,
};
static void __init bcm2709_timer_init(void)
{
/* init high res timer */
bcm2709_clocksource_init();
/*
* Make irqs happen for the system timer
*/
setup_irq(IRQ_TIMER3, &bcm2709_timer_irq);
sched_clock_register(bcm2709_read_sched_clock, 32, STC_FREQ_HZ);
timer0_clockevent.mult =
div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
timer0_clockevent.max_delta_ns =
clockevent_delta2ns(0xffffffff, &timer0_clockevent);
timer0_clockevent.min_delta_ns =
clockevent_delta2ns(0xf, &timer0_clockevent);
timer0_clockevent.cpumask = cpumask_of(0);
clockevents_register_device(&timer0_clockevent);
register_current_timer_delay(&bcm2709_delay_timer);
}
#else
static void __init bcm2709_timer_init(void)
{
extern void dc4_arch_timer_init(void);
// timer control
writel(0, __io_address(ARM_LOCAL_CONTROL));
// timer pre_scaler
writel(0x80000000, __io_address(ARM_LOCAL_PRESCALER)); // 19.2MHz
//writel(0x06AAAAAB, __io_address(ARM_LOCAL_PRESCALER)); // 1MHz
if (use_dt)
{
of_clk_init(NULL);
clocksource_of_init();
}
else
dc4_arch_timer_init();
}
#endif
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
#include <linux/leds.h>
static struct gpio_led bcm2709_leds[] = {
[0] = {
.gpio = 16,
.name = "led0",
.default_trigger = "mmc0",
.active_low = 1,
},
};
static struct gpio_led_platform_data bcm2709_led_pdata = {
.num_leds = ARRAY_SIZE(bcm2709_leds),
.leds = bcm2709_leds,
};
static struct platform_device bcm2709_led_device = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &bcm2709_led_pdata,
},
};
static void __init bcm2709_init_led(void)
{
bcm2709_leds[0].gpio = disk_led_gpio;
bcm2709_leds[0].active_low = disk_led_active_low;
bcm_register_device_dt(&bcm2709_led_device);
}
#else
static inline void bcm2709_init_led(void)
{
}
#endif
void __init bcm2709_init_early(void)
{
/*
* Some devices allocate their coherent buffers from atomic
* context. Increase size of atomic coherent pool to make sure such
* the allocations won't fail.
*/
init_dma_coherent_pool_size(SZ_4M);
}
static void __init board_reserve(void)
{
#if defined(CONFIG_BCM_VC_CMA)
vc_cma_reserve();
#endif
}
#ifdef CONFIG_SMP
#include <linux/smp.h>
#include <mach/hardware.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
int dc4=0;
//void dc4_log(unsigned x) { if (dc4) writel((x), __io_address(ST_BASE+10 + raw_smp_processor_id()*4)); }
void dc4_log_dead(unsigned x) { if (dc4) writel((readl(__io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)) & 0xffff) | ((x)<<16), __io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)); }
static void bcm2835_send_doorbell(const struct cpumask *mask, unsigned int irq)
{
int cpu;
/*
* Ensure that stores to Normal memory are visible to the
* other CPUs before issuing the IPI.
*/
dsb();
/* Convert our logical CPU mask into a physical one. */
for_each_cpu(cpu, mask)
{
/* submit softirq */
writel(1<<irq, __io_address(ARM_LOCAL_MAILBOX0_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0)));
}
}
void __init bcm2709_smp_init_cpus(void)
{
void secondary_startup(void);
unsigned int i, ncores;
ncores = 4; // xxx scu_get_core_count(NULL);
printk("[%s] enter (%x->%x)\n", __FUNCTION__, (unsigned)virt_to_phys((void *)secondary_startup), (unsigned)__io_address(ST_BASE + 0x10));
printk("[%s] ncores=%d\n", __FUNCTION__, ncores);
for (i = 0; i < ncores; i++) {
set_cpu_possible(i, true);
/* enable IRQ (not FIQ) */
writel(0x1, __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 0x4 * i));
//writel(0xf, __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 0x4 * i));
}
set_smp_cross_call(bcm2835_send_doorbell);
}
/*
* for arch/arm/kernel/smp.c:smp_prepare_cpus(unsigned int max_cpus)
*/
void __init bcm2709_smp_prepare_cpus(unsigned int max_cpus)
{
//void __iomem *scu_base;
printk("[%s] enter\n", __FUNCTION__);
//scu_base = scu_base_addr();
//scu_enable(scu_base);
}
/*
* for linux/arch/arm/kernel/smp.c:secondary_start_kernel(void)
*/
void __cpuinit bcm2709_secondary_init(unsigned int cpu)
{
printk("[%s] enter cpu:%d\n", __FUNCTION__, cpu);
//gic_secondary_init(0);
}
/*
* for linux/arch/arm/kernel/smp.c:__cpu_up(..)
*/
int __cpuinit bcm2709_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
void secondary_startup(void);
void *mbox_set = __io_address(ARM_LOCAL_MAILBOX3_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0));
void *mbox_clr = __io_address(ARM_LOCAL_MAILBOX3_CLR0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0));
unsigned secondary_boot = (unsigned)virt_to_phys((void *)secondary_startup);
int timeout=20;
unsigned t = -1;
//printk("[%s] enter cpu:%d (%x->%p) %x\n", __FUNCTION__, cpu, secondary_boot, wake, readl(wake));
dsb();
BUG_ON(readl(mbox_clr) != 0);
writel(secondary_boot, mbox_set);
while (--timeout > 0) {
t = readl(mbox_clr);
if (t == 0) break;
cpu_relax();
}
if (timeout==0)
printk("[%s] cpu:%d failed to start (%x)\n", __FUNCTION__, cpu, t);
else
printk("[%s] cpu:%d started (%x) %d\n", __FUNCTION__, cpu, t, timeout);
return 0;
}
struct smp_operations bcm2709_smp_ops __initdata = {
.smp_init_cpus = bcm2709_smp_init_cpus,
.smp_prepare_cpus = bcm2709_smp_prepare_cpus,
.smp_secondary_init = bcm2709_secondary_init,
.smp_boot_secondary = bcm2709_boot_secondary,
};
#endif
static const char * const bcm2709_compat[] = {
"brcm,bcm2709",
"brcm,bcm2708", /* Could use bcm2708 in a pinch */
NULL
};
MACHINE_START(BCM2709, "BCM2709")
/* Maintainer: Broadcom Europe Ltd. */
#ifdef CONFIG_SMP
.smp = smp_ops(bcm2709_smp_ops),
#endif
.map_io = bcm2709_map_io,
.init_irq = bcm2709_init_irq,
.init_time = bcm2709_timer_init,
.init_machine = bcm2709_init,
.init_early = bcm2709_init_early,
.reserve = board_reserve,
.restart = bcm2709_restart,
.dt_compat = bcm2709_compat,
MACHINE_END
MACHINE_START(BCM2708, "BCM2709")
/* Maintainer: Broadcom Europe Ltd. */
#ifdef CONFIG_SMP
.smp = smp_ops(bcm2709_smp_ops),
#endif
.map_io = bcm2709_map_io,
.init_irq = bcm2709_init_irq,
.init_time = bcm2709_timer_init,
.init_machine = bcm2709_init,
.init_early = bcm2709_init_early,
.reserve = board_reserve,
.restart = bcm2709_restart,
.dt_compat = bcm2709_compat,
MACHINE_END
module_param(boardrev, uint, 0644);
module_param(serial, uint, 0644);
module_param(uart_clock, uint, 0644);
module_param(disk_led_gpio, uint, 0644);
module_param(disk_led_active_low, uint, 0644);
module_param(reboot_part, uint, 0644);

49
arch/arm/mach-bcm2709/bcm2709.h Normal file
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@@ -0,0 +1,49 @@
/*
* linux/arch/arm/mach-bcm2708/bcm2708.h
*
* BCM2708 machine support header
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __BCM2708_BCM2708_H
#define __BCM2708_BCM2708_H
#include <linux/amba/bus.h>
extern void __init bcm2708_init(void);
extern void __init bcm2708_init_irq(void);
extern void __init bcm2708_map_io(void);
extern struct sys_timer bcm2708_timer;
extern unsigned int mmc_status(struct device *dev);
#define AMBA_DEVICE(name, busid, base, plat) \
static struct amba_device name##_device = { \
.dev = { \
.coherent_dma_mask = ~0, \
.init_name = busid, \
.platform_data = plat, \
}, \
.res = { \
.start = base##_BASE, \
.end = (base##_BASE) + SZ_4K - 1,\
.flags = IORESOURCE_MEM, \
}, \
.irq = base##_IRQ, \
}
#endif

21
arch/arm/mach-bcm2709/delay.S Normal file
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/*
* linux/arch/arm/lib/delay.S
*
* Copyright (C) 1995, 1996 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/param.h>
.text
.align 3 @ 8 byte alignment seems to be needed to avoid fetching stalls
@ Delay routine
ENTRY(bcm2708_delay)
subs r0, r0, #1
bhi bcm2708_delay
mov pc, lr
ENDPROC(bcm2708_delay)

493
arch/arm/mach-bcm2709/include/mach/arm_control.h Normal file
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/*
* linux/arch/arm/mach-bcm2708/arm_control.h
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __BCM2708_ARM_CONTROL_H
#define __BCM2708_ARM_CONTROL_H
/*
* Definitions and addresses for the ARM CONTROL logic
* This file is manually generated.
*/
#define ARM_BASE 0x7E00B000
/* Basic configuration */
#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000)
#define ARM_C0_SIZ128M 0x00000000
#define ARM_C0_SIZ256M 0x00000001
#define ARM_C0_SIZ512M 0x00000002
#define ARM_C0_SIZ1G 0x00000003
#define ARM_C0_BRESP0 0x00000000
#define ARM_C0_BRESP1 0x00000004
#define ARM_C0_BRESP2 0x00000008
#define ARM_C0_BOOTHI 0x00000010
#define ARM_C0_UNUSED05 0x00000020 /* free */
#define ARM_C0_FULLPERI 0x00000040
#define ARM_C0_UNUSED78 0x00000180 /* free */
#define ARM_C0_JTAGMASK 0x00000E00
#define ARM_C0_JTAGOFF 0x00000000
#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */
#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */
#define ARM_C0_APROTMSK 0x0000F000
#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */
#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */
#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */
#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */
#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */
#define ARM_C0_PRIO_L2 0x0F000000
#define ARM_C0_PRIO_UC 0xF0000000
#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */
#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */
#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */
#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440)
#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */
#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */
#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */
#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */
#define ARM_C1_PERSON 0x00000100 /* peripherals on */
#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */
#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444)
#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */
#define ARM_S_READPEND 0x000003FF /* pending reads counter */
#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */
#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448)
#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */
#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */
#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */
#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */
#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */
#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */
#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C)
#define ARM_IDVAL 0x364D5241
/* Translation memory */
#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
/* 32 locations: 0x100.. 0x17F */
/* 32 spare means we CAN go to 64 pages.... */
/* Interrupts */
#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */
#define ARM_I0_TIMER 0x00000001 /* timer IRQ */
#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */
#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */
#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */
#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */
#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */
#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
/* todo: all I1_interrupt sources */
#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
/* todo: all I2_interrupt sources */
#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
#define ARM_IF_INDEX 0x0000007F /* FIQ select */
#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */
#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */
#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */
#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */
#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */
#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */
#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */
#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */
#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */
#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */
#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */
#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */
#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */
#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */
#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */
#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */
/* Timer */
/* For reg. fields see sp804 spec. */
#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400)
#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404)
#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410)
#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414)
#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418)
#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c)
#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
#define TIMER_CTRL_ONESHOT (1 << 0)
#define TIMER_CTRL_32BIT (1 << 1)
#define TIMER_CTRL_DIV1 (0 << 2)
#define TIMER_CTRL_DIV16 (1 << 2)
#define TIMER_CTRL_DIV256 (2 << 2)
#define TIMER_CTRL_IE (1 << 5)
#define TIMER_CTRL_PERIODIC (1 << 6)
#define TIMER_CTRL_ENABLE (1 << 7)
#define TIMER_CTRL_DBGHALT (1 << 8)
#define TIMER_CTRL_ENAFREE (1 << 9)
#define TIMER_CTRL_FREEDIV_SHIFT 16)
#define TIMER_CTRL_FREEDIV_MASK 0xff
/* Semaphores, Doorbells, Mailboxes */
#define ARM_SBM_OWN0 (ARM_BASE+0x800)
#define ARM_SBM_OWN1 (ARM_BASE+0x900)
#define ARM_SBM_OWN2 (ARM_BASE+0xA00)
#define ARM_SBM_OWN3 (ARM_BASE+0xB00)
/* MAILBOXES
* Register flags are common across all
* owner registers. See end of this section
*
* Semaphores, Doorbells, Mailboxes Owner 0
*
*/
#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
/* MAILBOX 0 access in Owner 0 area */
/* Some addresses should ONLY be used by owner 0 */
#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */
#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */
#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */
#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */
#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */
#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */
/* MAILBOX 1 access in Owner 0 area */
/* Owner 0 should only WRITE to this mailbox */
#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */
/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */
/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
/* General SEM, BELL, MAIL config/status */
#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */
#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */
#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */
#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */
/* Semaphores, Doorbells, Mailboxes Owner 1 */
#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
/* MAILBOX 0 access in Owner 0 area */
/* Owner 1 should only WRITE to this mailbox */
#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */
/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */
/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
/* MAILBOX 1 access in Owner 0 area */
#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */
#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */
#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */
#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */
#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */
#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
/* General SEM, BELL, MAIL config/status */
#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */
#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */
#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */
#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */
/* Semaphores, Doorbells, Mailboxes Owner 2 */
#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
/* MAILBOX 0 access in Owner 2 area */
/* Owner 2 should only WRITE to this mailbox */
#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */
/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */
#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */
/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */
/* MAILBOX 1 access in Owner 2 area */
/* Owner 2 should only WRITE to this mailbox */
#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */
/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */
/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
/* General SEM, BELL, MAIL config/status */
#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */
#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */
#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */
#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */
/* Semaphores, Doorbells, Mailboxes Owner 3 */
#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
/* MAILBOX 0 access in Owner 3 area */
/* Owner 3 should only WRITE to this mailbox */
#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */
/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */
#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */
/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */
/* MAILBOX 1 access in Owner 3 area */
/* Owner 3 should only WRITE to this mailbox */
#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */
/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */
/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
/* General SEM, BELL, MAIL config/status */
#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */
#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */
#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */
#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */
/* Mailbox flags. Valid for all owners */
/* Mailbox status register (...0x98) */
#define ARM_MS_FULL 0x80000000
#define ARM_MS_EMPTY 0x40000000
#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */
/* MAILBOX config/status register (...0x9C) */
/* ANY write to this register clears the error bits! */
#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */
#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */
#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */
#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */
#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */
#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
/* Bit 7 is unused */
#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */
#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
/* Semaphore clear/debug register (...0xE0) */
#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */
#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */
#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */
#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */
#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */
#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */
#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */
#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */
#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */
#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */
#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */
#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */
#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */
#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */
#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */
#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */
/* Doorbells clear/debug register (...0xE4) */
#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */
#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */
#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */
#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */
#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */
#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */
#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */
#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */
/* MY IRQS register (...0xF8) */
#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */
#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */
/* ALL IRQS register (...0xF8) */
#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */
#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */
#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */
#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */
#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */
#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */
#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */
#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */
#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */
#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */
/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
/* */
/* ARM JTAG BASH */
/* */
#define AJB_BASE 0x7e2000c0
#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
#define AJB_BITS0 0x000000
#define AJB_BITS4 0x000004
#define AJB_BITS8 0x000008
#define AJB_BITS12 0x00000C
#define AJB_BITS16 0x000010
#define AJB_BITS20 0x000014
#define AJB_BITS24 0x000018
#define AJB_BITS28 0x00001C
#define AJB_BITS32 0x000020
#define AJB_BITS34 0x000022
#define AJB_OUT_MS 0x000040
#define AJB_OUT_LS 0x000000
#define AJB_INV_CLK 0x000080
#define AJB_D0_RISE 0x000100
#define AJB_D0_FALL 0x000000
#define AJB_D1_RISE 0x000200
#define AJB_D1_FALL 0x000000
#define AJB_IN_RISE 0x000400
#define AJB_IN_FALL 0x000000
#define AJB_ENABLE 0x000800
#define AJB_HOLD0 0x000000
#define AJB_HOLD1 0x001000
#define AJB_HOLD2 0x002000
#define AJB_HOLD3 0x003000
#define AJB_RESETN 0x004000
#define AJB_CLKSHFT 16
#define AJB_BUSY 0x80000000
#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
#define ARM_LOCAL_BASE 0x40000000
#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000)
#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008)
#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C)
#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010)
#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014)
#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C)
#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020)
#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024)
#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C)
#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030)
#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034)
#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038)
#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040)
#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044)
#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048)
#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C)
#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050)
#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054)
#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058)
#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C)
#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060)
#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064)
#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068)
#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C)
#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070)
#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074)
#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078)
#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C)
#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080)
#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084)
#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088)
#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C)
#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090)
#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094)
#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098)
#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C)
#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0)
#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4)
#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8)
#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC)
#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0)
#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4)
#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8)
#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC)
#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0)
#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4)
#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8)
#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC)
#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0)
#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4)
#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8)
#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC)
#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0)
#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4)
#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8)
#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC)
#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0)
#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4)
#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8)
#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC)
#endif

3
arch/arm/mach-bcm2709/include/mach/barriers.h Normal file
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@@ -0,0 +1,3 @@
#define mb() dsb()
#define rmb() dsb()
#define wmb() mb()

7
arch/arm/mach-bcm2709/include/mach/clkdev.h Normal file
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@@ -0,0 +1,7 @@
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

22
arch/arm/mach-bcm2709/include/mach/debug-macro.S Normal file
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@@ -0,0 +1,22 @@
/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 2010 Broadcom
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <mach/platform.h>
.macro addruart, rp, rv, tmp
ldr \rp, =UART0_BASE
ldr \rv, =IO_ADDRESS(UART0_BASE)
.endm
#include <debug/pl01x.S>

123
arch/arm/mach-bcm2709/include/mach/entry-macro.S Normal file
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@@ -0,0 +1,123 @@
/*
* arch/arm/mach-bcm2708/include/mach/entry-macro.S
*
* Low-level IRQ helper macros for BCM2708 platforms
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <mach/hardware.h>
#include <mach/irqs.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
/* get core number */
mrc p15, 0, \tmp, c0, c0, 5
ubfx \tmp, \tmp, #0, #2
/* get core's local interrupt controller */
ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source
add \irqstat, \irqstat, \tmp, lsl #2
ldr \tmp, [\irqstat]
/* ignore gpu interrupt */
bic \tmp, #0x100
/* ignore mailbox interrupts */
bics \tmp, #0xf0
beq 1005f
@ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
@ N.B. CLZ is an ARM5 instruction.
mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31)
sub \irqstat, \tmp, #1
eor \irqstat, \irqstat, \tmp
clz \tmp, \irqstat
sub \irqnr, \tmp
b 1020f
1005:
/* get core number */
mrc p15, 0, \tmp, c0, c0, 5
ubfx \tmp, \tmp, #0, #2
cmp \tmp, #1
beq 1020f
cmp \tmp, #2
beq 1020f
cmp \tmp, #3
beq 1020f
/* get masked status */
ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
mov \irqnr, #(ARM_IRQ0_BASE + 31)
and \tmp, \irqstat, #0x300 @ save bits 8 and 9
/* clear bits 8 and 9, and test */
bics \irqstat, \irqstat, #0x300
bne 1010f
tst \tmp, #0x100
ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
movne \irqnr, #(ARM_IRQ1_BASE + 31)
@ Mask out the interrupts also present in PEND0 - see SW-5809
bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
bicne \irqstat, #((1<<18) | (1<<19))
bne 1010f
tst \tmp, #0x200
ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
movne \irqnr, #(ARM_IRQ2_BASE + 31)
@ Mask out the interrupts also present in PEND0 - see SW-5809
bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
bicne \irqstat, #((1<<30))
beq 1020f
1010:
@ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
@ N.B. CLZ is an ARM5 instruction.
sub \tmp, \irqstat, #1
eor \irqstat, \irqstat, \tmp
clz \tmp, \irqstat
sub \irqnr, \tmp
1020: @ EQ will be set if no irqs pending
.endm
.macro test_for_ipi, irqnr, irqstat, base, tmp
/* get core number */
mrc p15, 0, \tmp, c0, c0, 5
ubfx \tmp, \tmp, #0, #2
/* get core's mailbox interrupt control */
ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr
add \irqstat, \irqstat, \tmp, lsl #4
ldr \tmp, [\irqstat]
cmp \tmp, #0
beq 1030f
clz \tmp, \tmp
rsb \irqnr, \tmp, #31
mov \tmp, #1
lsl \tmp, \irqnr
str \tmp, [\irqstat] @ clear interrupt source
dsb
1030: @ EQ will be set if no irqs pending
.endm

38
arch/arm/mach-bcm2709/include/mach/frc.h Normal file
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/*
* arch/arm/mach-bcm2708/include/mach/timex.h
*
* BCM2708 free running counter (timer)
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_FRC_H
#define _MACH_FRC_H
#define FRC_TICK_RATE (1000000)
/*! Free running counter incrementing at the CLOCK_TICK_RATE
(slightly faster than frc_clock_ticks63()
*/
extern unsigned long frc_clock_ticks32(void);
/*! Free running counter incrementing at the CLOCK_TICK_RATE
* Note - top bit should be ignored (see cnt32_to_63)
*/
extern unsigned long long frc_clock_ticks63(void);
#endif

17
arch/arm/mach-bcm2709/include/mach/gpio.h Normal file
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/*
* arch/arm/mach-bcm2708/include/mach/gpio.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H
#define BCM2708_NR_GPIOS 54 // number of gpio lines
#define gpio_to_irq(x) ((x) + GPIO_IRQ_START)
#define irq_to_gpio(x) ((x) - GPIO_IRQ_START)
#endif

28
arch/arm/mach-bcm2709/include/mach/hardware.h Normal file
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/*
* arch/arm/mach-bcm2708/include/mach/hardware.h
*
* This file contains the hardware definitions of the BCM2708 devices.
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/sizes.h>
#include <mach/platform.h>
#endif

27
arch/arm/mach-bcm2709/include/mach/io.h Normal file
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/*
* arch/arm/mach-bcm2708/include/mach/io.h
*
* Copyright (C) 2003 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) __typesafe_io(a)
#endif

225
arch/arm/mach-bcm2709/include/mach/irqs.h Normal file
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/*
* arch/arm/mach-bcm2708/include/mach/irqs.h
*
* Copyright (C) 2010 Broadcom
* Copyright (C) 2003 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _BCM2708_IRQS_H_
#define _BCM2708_IRQS_H_
#include <mach/platform.h>
/*
* IRQ interrupts definitions are the same as the INT definitions
* held within platform.h
*/
#define IRQ_ARMCTRL_START 0
#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP)
#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB)
#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D)
#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX)
#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM)
#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC)
#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE)
#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR)
#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI)
#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C)
#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI)
#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART)
#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC)
#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG)
#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG)
#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
#define IRQ_ARM_LOCAL_CNTPSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ)
#define IRQ_ARM_LOCAL_CNTPNSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ)
#define IRQ_ARM_LOCAL_CNTHPIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ)
#define IRQ_ARM_LOCAL_CNTVIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ)
#define IRQ_ARM_LOCAL_MAILBOX0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0)
#define IRQ_ARM_LOCAL_MAILBOX1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1)
#define IRQ_ARM_LOCAL_MAILBOX2 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2)
#define IRQ_ARM_LOCAL_MAILBOX3 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3)
#define IRQ_ARM_LOCAL_GPU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST)
#define IRQ_ARM_LOCAL_PMU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST)
#define IRQ_ARM_LOCAL_ZERO (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO)
#define IRQ_ARM_LOCAL_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER)
#define FIQ_START HARD_IRQS
/*
* FIQ interrupts definitions are the same as the INT definitions.
*/
#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0)
#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1)
#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2)
#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3)
#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0)
#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1)
#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2)
#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG)
#define FIQ_ISP (FIQ_START+INTERRUPT_ISP)
#define FIQ_USB (FIQ_START+INTERRUPT_USB)
#define FIQ_3D (FIQ_START+INTERRUPT_3D)
#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER)
#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0)
#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1)
#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2)
#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3)
#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0)
#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1)
#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2)
#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3)
#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4)
#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5)
#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6)
#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7)
#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8)
#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9)
#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10)
#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11)
#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12)
#define FIQ_AUX (FIQ_START+INTERRUPT_AUX)
#define FIQ_ARM (FIQ_START+INTERRUPT_ARM)
#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA)
#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT)
#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER)
#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX)
#define FIQ_SDC (FIQ_START+INTERRUPT_SDC)
#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0)
#define FIQ_AVE (FIQ_START+INTERRUPT_AVE)
#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0)
#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1)
#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0)
#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1)
#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1)
#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV)
#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1)
#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0)
#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1)
#define FIQ_CPR (FIQ_START+INTERRUPT_CPR)
#define FIQ_SMI (FIQ_START+INTERRUPT_SMI)
#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0)
#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1)
#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2)
#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3)
#define FIQ_I2C (FIQ_START+INTERRUPT_I2C)
#define FIQ_SPI (FIQ_START+INTERRUPT_SPI)
#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM)
#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO)
#define FIQ_UART (FIQ_START+INTERRUPT_UART)
#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS)
#define FIQ_VEC (FIQ_START+INTERRUPT_VEC)
#define FIQ_CPG (FIQ_START+INTERRUPT_CPG)
#define FIQ_RNG (FIQ_START+INTERRUPT_RNG)
#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO)
#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON)
#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER)
#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX)
#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0)
#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1)
#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED)
#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED)
#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0)
#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1)
#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1)
#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2)
#define FIQ_ARM_LOCAL_CNTPSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ)
#define FIQ_ARM_LOCAL_CNTPNSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ)
#define FIQ_ARM_LOCAL_CNTHPIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ)
#define FIQ_ARM_LOCAL_CNTVIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ)
#define FIQ_ARM_LOCAL_MAILBOX0 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0)
#define FIQ_ARM_LOCAL_MAILBOX1 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1)
#define FIQ_ARM_LOCAL_MAILBOX2 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2)
#define FIQ_ARM_LOCAL_MAILBOX3 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3)
#define FIQ_ARM_LOCAL_GPU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST)
#define FIQ_ARM_LOCAL_PMU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST)
#define FIQ_ARM_LOCAL_ZERO (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO)
#define FIQ_ARM_LOCAL_TIMER (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER)
#define HARD_IRQS (128)
#define FIQ_IRQS (128)
#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS)
#define GPIO_IRQS (32*5)
#define SPARE_ALLOC_IRQS 64
#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS)
#define FREE_IRQS 128
#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS)
#endif /* _BCM2708_IRQS_H_ */

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/*
* arch/arm/mach-bcm2708/include/mach/memory.h
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/* Memory overview:
[ARMcore] <--virtual addr-->
[ARMmmu] <--physical addr-->
[GERTmap] <--bus add-->
[VCperiph]
*/
/*
* Physical DRAM offset.
*/
#define BCM_PLAT_PHYS_OFFSET UL(0x00000000)
#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
#ifdef CONFIG_BCM2708_NOL2CACHE
#define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
#else
#define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
#endif
/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
* will provide the offset into this area as well as setting the bits that
* stop the L1 and L2 cache from being used
*
* WARNING: this only works because the ARM is given memory at a fixed location
* (ARMMEM_OFFSET)
*/
#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
#endif

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/*
* arch/arm/mach-bcm2708/include/mach/platform.h
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _BCM2708_PLATFORM_H
#define _BCM2708_PLATFORM_H
/* macros to get at IO space when running virtually */
#define IO_ADDRESS(x) (((x) & 0x00ffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
#define __io_address(n) IOMEM(IO_ADDRESS(n))
/*
* SDRAM
*/
#define BCM2708_SDRAM_BASE 0x00000000
/*
* Logic expansion modules
*
*/
/* ------------------------------------------------------------------------
* BCM2708 ARMCTRL Registers
* ------------------------------------------------------------------------
*/
#define HW_REGISTER_RW(addr) (addr)
#define HW_REGISTER_RO(addr) (addr)
#include "arm_control.h"
#undef ARM_BASE
/*
* Definitions and addresses for the ARM CONTROL logic
* This file is manually generated.
*/
#define BCM2708_PERI_BASE 0x3F000000
#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
#define ARMCTRL_BASE (ARM_BASE + 0x000)
#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
/*
* Interrupt assignments
*/
#define ARM_IRQ1_BASE 0
#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0)
#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1)
#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2)
#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3)
#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4)
#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5)
#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6)
#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7)
#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8)
#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9)
#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10)
#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11)
#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12)
#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13)
#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14)
#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15)
#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16)
#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17)
#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18)
#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19)
#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20)
#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21)
#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22)
#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23)
#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24)
#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25)
#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26)
#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27)
#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28)
#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29)
#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30)
#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31)
#define ARM_IRQ2_BASE 32
#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0)
#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1)
#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2)
#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3)
#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4)
#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5)
#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6)
#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7)
#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8)
#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9)
#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10)
#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11)
#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12)
#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13)
#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14)
#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15)
#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16)
#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17)
#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18)
#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19)
#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20)
#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21)
#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22)
#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23)
#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24)
#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25)
#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26)
#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27)
#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28)
#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29)
#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30)
#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31)
#define ARM_IRQ0_BASE 64
#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0)
#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1)
#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2)
#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3)
#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4)
#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5)
#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6)
#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7)
#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8)
#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9)
#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10)
#define INTERRUPT_USB (ARM_IRQ0_BASE + 11)
#define INTERRUPT_3D (ARM_IRQ0_BASE + 12)
#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13)
#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14)
#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15)
#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16)
#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17)
#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18)
#define INTERRUPT_UART (ARM_IRQ0_BASE + 19)
#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20)
#define ARM_IRQ_LOCAL_BASE 96
#define INTERRUPT_ARM_LOCAL_CNTPSIRQ (ARM_IRQ_LOCAL_BASE + 0)
#define INTERRUPT_ARM_LOCAL_CNTPNSIRQ (ARM_IRQ_LOCAL_BASE + 1)
#define INTERRUPT_ARM_LOCAL_CNTHPIRQ (ARM_IRQ_LOCAL_BASE + 2)
#define INTERRUPT_ARM_LOCAL_CNTVIRQ (ARM_IRQ_LOCAL_BASE + 3)
#define INTERRUPT_ARM_LOCAL_MAILBOX0 (ARM_IRQ_LOCAL_BASE + 4)
#define INTERRUPT_ARM_LOCAL_MAILBOX1 (ARM_IRQ_LOCAL_BASE + 5)
#define INTERRUPT_ARM_LOCAL_MAILBOX2 (ARM_IRQ_LOCAL_BASE + 6)
#define INTERRUPT_ARM_LOCAL_MAILBOX3 (ARM_IRQ_LOCAL_BASE + 7)
#define INTERRUPT_ARM_LOCAL_GPU_FAST (ARM_IRQ_LOCAL_BASE + 8)
#define INTERRUPT_ARM_LOCAL_PMU_FAST (ARM_IRQ_LOCAL_BASE + 9)
#define INTERRUPT_ARM_LOCAL_ZERO (ARM_IRQ_LOCAL_BASE + 10)
#define INTERRUPT_ARM_LOCAL_TIMER (ARM_IRQ_LOCAL_BASE + 11)
/*
* Watchdog
*/
#define PM_RSTC (PM_BASE+0x1c)
#define PM_RSTS (PM_BASE+0x20)
#define PM_WDOG (PM_BASE+0x24)
#define PM_WDOG_RESET 0000000000
#define PM_PASSWORD 0x5a000000
#define PM_WDOG_TIME_SET 0x000fffff
#define PM_RSTC_WRCFG_CLR 0xffffffcf
#define PM_RSTC_WRCFG_SET 0x00000030
#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
#define PM_RSTC_RESET 0x00000102
#define PM_RSTS_HADPOR_SET 0x00001000
#define PM_RSTS_HADSRH_SET 0x00000400
#define PM_RSTS_HADSRF_SET 0x00000200
#define PM_RSTS_HADSRQ_SET 0x00000100
#define PM_RSTS_HADWRH_SET 0x00000040
#define PM_RSTS_HADWRF_SET 0x00000020
#define PM_RSTS_HADWRQ_SET 0x00000010
#define PM_RSTS_HADDRH_SET 0x00000004
#define PM_RSTS_HADDRF_SET 0x00000002
#define PM_RSTS_HADDRQ_SET 0x00000001
#define UART0_CLOCK 3000000
#endif
/* END */

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/*
* arch/arm/mach-bcm2708/include/mach/system.h
*
* Copyright (C) 2010 Broadcom
* Copyright (C) 2003 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/platform.h>
static inline void arch_idle(void)
{
/*
* This should do all the clock switching
* and wait for interrupt tricks
*/
cpu_do_idle();
}
#endif

23
arch/arm/mach-bcm2709/include/mach/timex.h Normal file
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/*
* arch/arm/mach-bcm2708/include/mach/timex.h
*
* BCM2708 sysem clock frequency
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define CLOCK_TICK_RATE (1000000)

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arch/arm/mach-bcm2709/include/mach/uncompress.h Normal file
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/*
* arch/arm/mach-bcn2708/include/mach/uncompress.h
*
* Copyright (C) 2010 Broadcom
* Copyright (C) 2003 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/io.h>
#include <linux/amba/serial.h>
#include <mach/hardware.h>
#define UART_BAUD 115200
#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
/*
* This does not append a newline
*/
static inline void putc(int c)
{
while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
barrier();
__raw_writel(c, BCM2708_UART_DR);
}
static inline void flush(void)
{
int fr;
do {
fr = __raw_readl(BCM2708_UART_FR);
barrier();
} while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
}
static inline void arch_decomp_setup(void)
{
int temp, div, rem, frac;
temp = 16 * UART_BAUD;
div = UART0_CLOCK / temp;
rem = UART0_CLOCK % temp;
temp = (8 * rem) / UART_BAUD;
frac = (temp >> 1) + (temp & 1);
/* Make sure the UART is disabled before we start */
__raw_writel(0, BCM2708_UART_CR);
/* Set the baud rate */
__raw_writel(div, BCM2708_UART_IBRD);
__raw_writel(frac, BCM2708_UART_FBRD);
/* Set the UART to 8n1, FIFO enabled */
__raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
/* Enable the UART */
__raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
BCM2708_UART_CR);
}
/*
* nothing to do
*/
#define arch_decomp_wdog()

35
arch/arm/mach-bcm2709/include/mach/vc_mem.h Normal file
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/*****************************************************************************
* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#if !defined( VC_MEM_H )
#define VC_MEM_H
#include <linux/ioctl.h>
#define VC_MEM_IOC_MAGIC 'v'
#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
#if defined( __KERNEL__ )
#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
extern unsigned long mm_vc_mem_phys_addr;
extern unsigned int mm_vc_mem_size;
extern int vc_mem_get_current_size( void );
#endif
#endif /* VC_MEM_H */

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#ifndef _VC_SUPPORT_H_
#define _VC_SUPPORT_H_
/*
* vc_support.h
*
* Created on: 25 Nov 2012
* Author: Simon
*/
enum {
/*
If a MEM_HANDLE_T is discardable, the memory manager may resize it to size
0 at any time when it is not locked or retained.
*/
MEM_FLAG_DISCARDABLE = 1 << 0,
/*
If a MEM_HANDLE_T is allocating (or normal), its block of memory will be
accessed in an allocating fashion through the cache.
*/
MEM_FLAG_NORMAL = 0 << 2,
MEM_FLAG_ALLOCATING = MEM_FLAG_NORMAL,
/*
If a MEM_HANDLE_T is direct, its block of memory will be accessed
directly, bypassing the cache.
*/
MEM_FLAG_DIRECT = 1 << 2,
/*
If a MEM_HANDLE_T is coherent, its block of memory will be accessed in a
non-allocating fashion through the cache.
*/
MEM_FLAG_COHERENT = 2 << 2,
/*
If a MEM_HANDLE_T is L1-nonallocating, its block of memory will be accessed by
the VPU in a fashion which is allocating in L2, but only coherent in L1.
*/
MEM_FLAG_L1_NONALLOCATING = (MEM_FLAG_DIRECT | MEM_FLAG_COHERENT),
/*
If a MEM_HANDLE_T is zero'd, its contents are set to 0 rather than
MEM_HANDLE_INVALID on allocation and resize up.
*/
MEM_FLAG_ZERO = 1 << 4,
/*
If a MEM_HANDLE_T is uninitialised, it will not be reset to a defined value
(either zero, or all 1's) on allocation.
*/
MEM_FLAG_NO_INIT = 1 << 5,
/*
Hints.
*/
MEM_FLAG_HINT_PERMALOCK = 1 << 6, /* Likely to be locked for long periods of time. */
};
unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags);
unsigned int ReleaseVcMemory(unsigned int handle);
unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle);
unsigned int UnlockVcMemory(unsigned int handle);
unsigned int ExecuteVcCode(unsigned int code,
unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5);
#endif

20
arch/arm/mach-bcm2709/include/mach/vmalloc.h Normal file
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/*
* arch/arm/mach-bcm2708/include/mach/vmalloc.h
*
* Copyright (C) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define VMALLOC_END (0xff000000)

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arch/arm/mach-bcm2709/vc_mem.c Normal file
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/*****************************************************************************
* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/fs.h>
#include <linux/device.h>
#include <linux/cdev.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/debugfs.h>
#include <asm/uaccess.h>
#include <linux/dma-mapping.h>
#include <linux/platform_data/mailbox-bcm2708.h>
#ifdef CONFIG_ARCH_KONA
#include <chal/chal_ipc.h>
#elif defined(CONFIG_ARCH_BCM2708) || defined(CONFIG_ARCH_BCM2709)
#else
#include <csp/chal_ipc.h>
#endif
#include "mach/vc_mem.h"
#define DRIVER_NAME "vc-mem"
// Device (/dev) related variables
static dev_t vc_mem_devnum = 0;
static struct class *vc_mem_class = NULL;
static struct cdev vc_mem_cdev;
static int vc_mem_inited = 0;
#ifdef CONFIG_DEBUG_FS
static struct dentry *vc_mem_debugfs_entry;
#endif
/*
* Videocore memory addresses and size
*
* Drivers that wish to know the videocore memory addresses and sizes should
* use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
* headers. This allows the other drivers to not be tied down to a a certain
* address/size at compile time.
*
* In the future, the goal is to have the videocore memory virtual address and
* size be calculated at boot time rather than at compile time. The decision of
* where the videocore memory resides and its size would be in the hands of the
* bootloader (and/or kernel). When that happens, the values of these variables
* would be calculated and assigned in the init function.
*/
// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
unsigned long mm_vc_mem_phys_addr = 0x00000000;
unsigned int mm_vc_mem_size = 0;
unsigned int mm_vc_mem_base = 0;
EXPORT_SYMBOL(mm_vc_mem_phys_addr);
EXPORT_SYMBOL(mm_vc_mem_size);
EXPORT_SYMBOL(mm_vc_mem_base);
static uint phys_addr = 0;
static uint mem_size = 0;
static uint mem_base = 0;
/****************************************************************************
*
* vc_mem_open
*
***************************************************************************/
static int
vc_mem_open(struct inode *inode, struct file *file)
{
(void) inode;
(void) file;
pr_debug("%s: called file = 0x%p\n", __func__, file);
return 0;
}
/****************************************************************************
*
* vc_mem_release
*
***************************************************************************/
static int
vc_mem_release(struct inode *inode, struct file *file)
{
(void) inode;
(void) file;
pr_debug("%s: called file = 0x%p\n", __func__, file);
return 0;
}
/****************************************************************************
*
* vc_mem_get_size
*
***************************************************************************/
static void
vc_mem_get_size(void)
{
}
/****************************************************************************
*
* vc_mem_get_base
*
***************************************************************************/
static void
vc_mem_get_base(void)
{
}
/****************************************************************************
*
* vc_mem_get_current_size
*
***************************************************************************/
int
vc_mem_get_current_size(void)
{
return mm_vc_mem_size;
}
EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
/****************************************************************************
*
* vc_mem_ioctl
*
***************************************************************************/
static long
vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
int rc = 0;
(void) cmd;
(void) arg;
pr_debug("%s: called file = 0x%p\n", __func__, file);
switch (cmd) {
case VC_MEM_IOC_MEM_PHYS_ADDR:
{
pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n",
__func__, (void *) mm_vc_mem_phys_addr);
if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
sizeof (mm_vc_mem_phys_addr)) != 0) {
rc = -EFAULT;
}
break;
}
case VC_MEM_IOC_MEM_SIZE:
{
// Get the videocore memory size first
vc_mem_get_size();
pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__,
mm_vc_mem_size);
if (copy_to_user((void *) arg, &mm_vc_mem_size,
sizeof (mm_vc_mem_size)) != 0) {
rc = -EFAULT;
}
break;
}
case VC_MEM_IOC_MEM_BASE:
{
// Get the videocore memory base
vc_mem_get_base();
pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__,
mm_vc_mem_base);
if (copy_to_user((void *) arg, &mm_vc_mem_base,
sizeof (mm_vc_mem_base)) != 0) {
rc = -EFAULT;
}
break;
}
case VC_MEM_IOC_MEM_LOAD:
{
// Get the videocore memory base
vc_mem_get_base();
pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__,
mm_vc_mem_base);
if (copy_to_user((void *) arg, &mm_vc_mem_base,
sizeof (mm_vc_mem_base)) != 0) {
rc = -EFAULT;
}
break;
}
default:
{
return -ENOTTY;
}
}
pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc);
return rc;
}
/****************************************************************************
*
* vc_mem_mmap
*
***************************************************************************/
static int
vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
{
int rc = 0;
unsigned long length = vma->vm_end - vma->vm_start;
unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n",
__func__, (long) vma->vm_start, (long) vma->vm_end,
(long) vma->vm_pgoff);
if (offset + length > mm_vc_mem_size) {
pr_err("%s: length %ld is too big\n", __func__, length);
return -EINVAL;
}
// Do not cache the memory map
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
rc = remap_pfn_range(vma, vma->vm_start,
(mm_vc_mem_phys_addr >> PAGE_SHIFT) +
vma->vm_pgoff, length, vma->vm_page_prot);
if (rc != 0) {
pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc);
}
return rc;
}
/****************************************************************************
*
* File Operations for the driver.
*
***************************************************************************/
static const struct file_operations vc_mem_fops = {
.owner = THIS_MODULE,
.open = vc_mem_open,
.release = vc_mem_release,
.unlocked_ioctl = vc_mem_ioctl,
.mmap = vc_mem_mmap,
};
#ifdef CONFIG_DEBUG_FS
static void vc_mem_debugfs_deinit(void)
{
debugfs_remove_recursive(vc_mem_debugfs_entry);
vc_mem_debugfs_entry = NULL;
}
static int vc_mem_debugfs_init(
struct device *dev)
{
vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL);
if (!vc_mem_debugfs_entry) {
dev_warn(dev, "could not create debugfs entry\n");
return -EFAULT;
}
if (!debugfs_create_x32("vc_mem_phys_addr",
0444,
vc_mem_debugfs_entry,
(u32 *)&mm_vc_mem_phys_addr)) {
dev_warn(dev, "%s:could not create vc_mem_phys entry\n",
__func__);
goto fail;
}
if (!debugfs_create_x32("vc_mem_size",
0444,
vc_mem_debugfs_entry,
(u32 *)&mm_vc_mem_size)) {
dev_warn(dev, "%s:could not create vc_mem_size entry\n",
__func__);
goto fail;
}
if (!debugfs_create_x32("vc_mem_base",
0444,
vc_mem_debugfs_entry,
(u32 *)&mm_vc_mem_base)) {
dev_warn(dev, "%s:could not create vc_mem_base entry\n",
__func__);
goto fail;
}
return 0;
fail:
vc_mem_debugfs_deinit();
return -EFAULT;
}
#endif /* CONFIG_DEBUG_FS */
/****************************************************************************
*
* vc_mem_init
*
***************************************************************************/
static int __init
vc_mem_init(void)
{
int rc = -EFAULT;
struct device *dev;
pr_debug("%s: called\n", __func__);
mm_vc_mem_phys_addr = phys_addr;
mm_vc_mem_size = mem_size;
mm_vc_mem_base = mem_base;
vc_mem_get_size();
pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
pr_err("%s: alloc_chrdev_region failed (rc=%d)\n",
__func__, rc);
goto out_err;
}
cdev_init(&vc_mem_cdev, &vc_mem_fops);
if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc);
goto out_unregister;
}
vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
if (IS_ERR(vc_mem_class)) {
rc = PTR_ERR(vc_mem_class);
pr_err("%s: class_create failed (rc=%d)\n", __func__, rc);
goto out_cdev_del;
}
dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
DRIVER_NAME);
if (IS_ERR(dev)) {
rc = PTR_ERR(dev);
pr_err("%s: device_create failed (rc=%d)\n", __func__, rc);
goto out_class_destroy;
}
#ifdef CONFIG_DEBUG_FS
/* don't fail if the debug entries cannot be created */
vc_mem_debugfs_init(dev);
#endif
vc_mem_inited = 1;
return 0;
device_destroy(vc_mem_class, vc_mem_devnum);
out_class_destroy:
class_destroy(vc_mem_class);
vc_mem_class = NULL;
out_cdev_del:
cdev_del(&vc_mem_cdev);
out_unregister:
unregister_chrdev_region(vc_mem_devnum, 1);
out_err:
return -1;
}
/****************************************************************************
*
* vc_mem_exit
*
***************************************************************************/
static void __exit
vc_mem_exit(void)
{
pr_debug("%s: called\n", __func__);
if (vc_mem_inited) {
#if CONFIG_DEBUG_FS
vc_mem_debugfs_deinit();
#endif
device_destroy(vc_mem_class, vc_mem_devnum);
class_destroy(vc_mem_class);
cdev_del(&vc_mem_cdev);
unregister_chrdev_region(vc_mem_devnum, 1);
}
}
module_init(vc_mem_init);
module_exit(vc_mem_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Broadcom Corporation");
module_param(phys_addr, uint, 0644);
module_param(mem_size, uint, 0644);
module_param(mem_base, uint, 0644);

318
arch/arm/mach-bcm2709/vc_support.c Normal file
View File

@@ -0,0 +1,318 @@
/*
* vc_support.c
*
* Created on: 25 Nov 2012
* Author: Simon
*/
#include <linux/module.h>
#include <linux/platform_data/mailbox-bcm2708.h>
#ifdef ECLIPSE_IGNORE
#define __user
#define __init
#define __exit
#define __iomem
#define KERN_DEBUG
#define KERN_ERR
#define KERN_WARNING
#define KERN_INFO
#define _IOWR(a, b, c) b
#define _IOW(a, b, c) b
#define _IO(a, b) b
#endif
/****** VC MAILBOX FUNCTIONALITY ******/
unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags)
{
struct vc_msg
{
unsigned int m_msgSize;
unsigned int m_response;
struct vc_tag
{
unsigned int m_tagId;
unsigned int m_sendBufferSize;
union {
unsigned int m_sendDataSize;
unsigned int m_recvDataSize;
};
struct args
{
union {
unsigned int m_size;
unsigned int m_handle;
};
unsigned int m_alignment;
unsigned int m_flags;
} m_args;
} m_tag;
unsigned int m_endTag;
} msg;
int s;
msg.m_msgSize = sizeof(msg);
msg.m_response = 0;
msg.m_endTag = 0;
//fill in the tag for the allocation command
msg.m_tag.m_tagId = 0x3000c;
msg.m_tag.m_sendBufferSize = 12;
msg.m_tag.m_sendDataSize = 12;
//fill in our args
msg.m_tag.m_args.m_size = size;
msg.m_tag.m_args.m_alignment = alignment;
msg.m_tag.m_args.m_flags = flags;
//run the command
s = bcm_mailbox_property(&msg, sizeof(msg));
if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
{
*pHandle = msg.m_tag.m_args.m_handle;
return 0;
}
else
{
printk(KERN_ERR "failed to allocate vc memory: s=%d response=%08x recv data size=%08x\n",
s, msg.m_response, msg.m_tag.m_recvDataSize);
return 1;
}
}
unsigned int ReleaseVcMemory(unsigned int handle)
{
struct vc_msg
{
unsigned int m_msgSize;
unsigned int m_response;
struct vc_tag
{
unsigned int m_tagId;
unsigned int m_sendBufferSize;
union {
unsigned int m_sendDataSize;
unsigned int m_recvDataSize;
};
struct args
{
union {
unsigned int m_handle;
unsigned int m_error;
};
} m_args;
} m_tag;
unsigned int m_endTag;
} msg;
int s;
msg.m_msgSize = sizeof(msg);
msg.m_response = 0;
msg.m_endTag = 0;
//fill in the tag for the release command
msg.m_tag.m_tagId = 0x3000f;
msg.m_tag.m_sendBufferSize = 4;
msg.m_tag.m_sendDataSize = 4;
//pass across the handle
msg.m_tag.m_args.m_handle = handle;
s = bcm_mailbox_property(&msg, sizeof(msg));
if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0)
return 0;
else
{
printk(KERN_ERR "failed to release vc memory: s=%d response=%08x recv data size=%08x error=%08x\n",
s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error);
return 1;
}
}
unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle)
{
struct vc_msg
{
unsigned int m_msgSize;
unsigned int m_response;
struct vc_tag
{
unsigned int m_tagId;
unsigned int m_sendBufferSize;
union {
unsigned int m_sendDataSize;
unsigned int m_recvDataSize;
};
struct args
{
union {
unsigned int m_handle;
unsigned int m_busAddress;
};
} m_args;
} m_tag;
unsigned int m_endTag;
} msg;
int s;
msg.m_msgSize = sizeof(msg);
msg.m_response = 0;
msg.m_endTag = 0;
//fill in the tag for the lock command
msg.m_tag.m_tagId = 0x3000d;
msg.m_tag.m_sendBufferSize = 4;
msg.m_tag.m_sendDataSize = 4;
//pass across the handle
msg.m_tag.m_args.m_handle = handle;
s = bcm_mailbox_property(&msg, sizeof(msg));
if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
{
//pick out the bus address
*pBusAddress = msg.m_tag.m_args.m_busAddress;
return 0;
}
else
{
printk(KERN_ERR "failed to lock vc memory: s=%d response=%08x recv data size=%08x\n",
s, msg.m_response, msg.m_tag.m_recvDataSize);
return 1;
}
}
unsigned int UnlockVcMemory(unsigned int handle)
{
struct vc_msg
{
unsigned int m_msgSize;
unsigned int m_response;
struct vc_tag
{
unsigned int m_tagId;
unsigned int m_sendBufferSize;
union {
unsigned int m_sendDataSize;
unsigned int m_recvDataSize;
};
struct args
{
union {
unsigned int m_handle;
unsigned int m_error;
};
} m_args;
} m_tag;
unsigned int m_endTag;
} msg;
int s;
msg.m_msgSize = sizeof(msg);
msg.m_response = 0;
msg.m_endTag = 0;
//fill in the tag for the unlock command
msg.m_tag.m_tagId = 0x3000e;
msg.m_tag.m_sendBufferSize = 4;
msg.m_tag.m_sendDataSize = 4;
//pass across the handle
msg.m_tag.m_args.m_handle = handle;
s = bcm_mailbox_property(&msg, sizeof(msg));
//check the error code too
if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0)
return 0;
else
{
printk(KERN_ERR "failed to unlock vc memory: s=%d response=%08x recv data size=%08x error%08x\n",
s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error);
return 1;
}
}
unsigned int ExecuteVcCode(unsigned int code,
unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5)
{
struct vc_msg
{
unsigned int m_msgSize;
unsigned int m_response;
struct vc_tag
{
unsigned int m_tagId;
unsigned int m_sendBufferSize;
union {
unsigned int m_sendDataSize;
unsigned int m_recvDataSize;
};
struct args
{
union {
unsigned int m_pCode;
unsigned int m_return;
};
unsigned int m_r0;
unsigned int m_r1;
unsigned int m_r2;
unsigned int m_r3;
unsigned int m_r4;
unsigned int m_r5;
} m_args;
} m_tag;
unsigned int m_endTag;
} msg;
int s;
msg.m_msgSize = sizeof(msg);
msg.m_response = 0;
msg.m_endTag = 0;
//fill in the tag for the unlock command
msg.m_tag.m_tagId = 0x30010;
msg.m_tag.m_sendBufferSize = 28;
msg.m_tag.m_sendDataSize = 28;
//pass across the handle
msg.m_tag.m_args.m_pCode = code;
msg.m_tag.m_args.m_r0 = r0;
msg.m_tag.m_args.m_r1 = r1;
msg.m_tag.m_args.m_r2 = r2;
msg.m_tag.m_args.m_r3 = r3;
msg.m_tag.m_args.m_r4 = r4;
msg.m_tag.m_args.m_r5 = r5;
s = bcm_mailbox_property(&msg, sizeof(msg));
//check the error code too
if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
return msg.m_tag.m_args.m_return;
else
{
printk(KERN_ERR "failed to execute: s=%d response=%08x recv data size=%08x\n",
s, msg.m_response, msg.m_tag.m_recvDataSize);
return 1;
}
}

2
arch/arm/mm/Kconfig
View File

@@ -358,7 +358,7 @@ config CPU_PJ4B
# ARMv6
config CPU_V6
bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708)
select CPU_32v6
select CPU_ABRT_EV6
select CPU_CACHE_V6

15
arch/arm/mm/proc-v6.S
View File

@@ -73,10 +73,19 @@ ENDPROC(cpu_v6_reset)
*
* IRQs are already disabled.
*/
/* See jira SW-5991 for details of this workaround */
ENTRY(cpu_v6_do_idle)
mov r1, #0
mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
.align 5
mov r1, #2
1: subs r1, #1
nop
mcreq p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
mcreq p15, 0, r1, c7, c0, 4 @ wait for interrupt
nop
nop
nop
bne 1b
ret lr
ENTRY(cpu_v6_dcache_clean_area)

1
arch/arm/mm/proc-v7.S
View File

@@ -460,6 +460,7 @@ __v7_setup_cont:
orr r0, r0, r6 @ set them
THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
ret lr @ return to head.S:__ret
.space 256
ENDPROC(__v7_setup)
.align 2

2
arch/arm/tools/mach-types
View File

@@ -522,6 +522,8 @@ torbreck MACH_TORBRECK TORBRECK 3090
prima2_evb MACH_PRIMA2_EVB PRIMA2_EVB 3103
paz00 MACH_PAZ00 PAZ00 3128
acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129
bcm2708 MACH_BCM2708 BCM2708 3138
bcm2709 MACH_BCM2709 BCM2709 3139
ag5evm MACH_AG5EVM AG5EVM 3189
ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206
wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207

36
drivers/clocksource/arm_arch_timer.c
View File

@@ -882,3 +882,39 @@ void __init acpi_generic_timer_init(void)
acpi_table_parse(ACPI_SIG_GTDT, arch_timer_acpi_init);
}
#endif
int __init dc4_arch_timer_init(void)
{
if (arch_timers_present & ARCH_CP15_TIMER) {
pr_warn("arch_timer: multiple nodes in dt, skipping\n");
return -1;
}
arch_timers_present |= ARCH_CP15_TIMER;
/* Try to determine the frequency from the device tree or CNTFRQ */
arch_timer_rate = 19200000;
arch_timer_ppi[PHYS_SECURE_PPI] = IRQ_ARM_LOCAL_CNTPSIRQ;
arch_timer_ppi[PHYS_NONSECURE_PPI] = IRQ_ARM_LOCAL_CNTPNSIRQ;
arch_timer_ppi[VIRT_PPI] = IRQ_ARM_LOCAL_CNTVIRQ;
arch_timer_ppi[HYP_PPI] = IRQ_ARM_LOCAL_CNTHPIRQ;
/*
* If HYP mode is available, we know that the physical timer
* has been configured to be accessible from PL1. Use it, so
* that a guest can use the virtual timer instead.
*
* If no interrupt provided for virtual timer, we'll have to
* stick to the physical timer. It'd better be accessible...
*/
if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
arch_timer_use_virtual = false;
}
arch_timer_c3stop = 0;
arch_timer_register();
arch_timer_common_init();
return 0;
}

2
drivers/tty/serial/amba-pl011.c
View File

@@ -85,7 +85,7 @@ struct vendor_data {
static unsigned int get_fifosize_arm(struct amba_device *dev)
{
return amba_rev(dev) < 3 ? 16 : 32;
return 16; //TODO: fix: amba_rev(dev) < 3 ? 16 : 32;
}
static struct vendor_data vendor_arm = {

1
include/linux/mmc/host.h
View File

@@ -285,6 +285,7 @@ struct mmc_host {
MMC_CAP2_HS400_1_2V)
#define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V)
#define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
#define MMC_CAP2_FORCE_MULTIBLOCK (1 << 31) /* Always use multiblock transfers */
mmc_pm_flag_t pm_caps; /* supported pm features */