The documentation only mentioned the generic fallback compatible
property.
Add the missing SoC-specific compatible properties, which are already in
use.
Also drop a bogus 0x unit-address prefix while we're at it.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mark Brown <broonie@kernel.org>
The documentation only mentioned the generic fallback compatible
property.
Add the missing SoC-specific compatible properties, some of which are
already in use.
Also fix a small typo, while we're at it.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mark Brown <broonie@kernel.org>
Enable led-mode configuration for KSZ8081 and KSZ8091.
Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
A recent commit extended the documentation of the ethernet-phy
compatible property, but placed the new paragraph under the max-speed
property.
Fixes: f00e756ed1 ("dt: Document a compatible entry for MDIO ethernet
Phys")
Cc: devicetree@vger.kernel.org
Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Make it possible to transfer i2c message buffers via DMA.
Start/Stop/Sending_Slave_Address is still handled using the old state
machine, it is sending the actual data that is done via DMA. This is
least intrusive and allows us to work with the message buffers directly
instead of preparing a custom buffer which involves copying the data
around.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
[wsa: fixed an uninitialized var problem]
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
An underrun (playback) event occurs when the serializer transfer
data from the XRBUF buffer to the XRSR shift register, but the
XRBUF hasn't been filled. Similarly, the overrun (capture) event
occurs when data from the XRSR shift register is transferred to
the XRBUF but it hasn't been read yet.
These events are handled as XRUN events that cause the pcm to stop.
The stream has to be explicitly restarted by the userspace which
ensures that after stopping/starting McASP the data transfer is
aligned with DMA. The other possibility was to internally stop and
start McASP without DMA even knowing about it.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This patch to compensate tx impedance (Sata, PCIe)
depending on Soc cuts the kernel is built for.
Signed-off-by: Giuseppe Condorelli <giuseppe.condorelli@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This patch to tune on/off the ssc on miphy sata setup.
User can now enable ssc via dt blob, it is useful to reduce
effects of EMI.
Signed-off-by: Giuseppe Condorelli <giuseppe.condorelli@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
It is not possible to auto detect the irq numbers used by the cores on
an arm SoC. If bcma was registered with device tree it will search for
some device tree nodes with the irq number and add it to the core
configuration.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit unifies the APB1 mux with the APB1 clock, using the new
factors infrastructure.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
[wens@csie.org: Add mux mask bits]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This driver has no 'compatible' string and so is not found when
using device-tree.
Add one with value to match
hdqw1w: 1w@480b2000 {
device in omap3.dtsi.
Signed-off-by: NeilBrown <neilb@suse.de>
Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Now that sdhci-pxav3 driver allows to have more than one IP clock defined,
document both clocks and clock-names properties.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Explicitly list the various SoC-specific compatible properties.
This allows checkpatch to validate DTSes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Exynos7 uses different offsets for wakeup interrupt configuration registers.
So a new irq_chip instance for Exynos7 wakeup interrupts is added. The irq_chip
selection is now based on the wakeup interrupt controller compatible string.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Most implementations of the bcm7120-l2 controller only have a single
32-bit enable word + 32-bit status word. But some instances have added
more enable/status pairs in order to support 64+ IRQs (which are all
ORed into one parent IRQ input). Make the following changes to allow
the driver to support this:
- Extend DT bindings so that multiple words can be specified for the
reg property, various masks, etc.
- Add loops to the probe/handle functions to deal with each word
separately
- Allocate 1 generic-chip for every 32 IRQs, so we can still use the
clr/set helper functions
- Update the documentation
This uses one domain per bcm7120-l2 DT node. If the DT node defines
multiple enable/status pairs (i.e. >=64 IRQs) then the driver will
create a single IRQ domain with 2+ generic chips. Multiple generic chips
are required because the generic-chip code can only handle one
enable/status register pair per instance.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lkml.kernel.org/r/1415342669-30640-12-git-send-email-cernekee@gmail.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Merge "Nomadik updates for the v3.19 series" from Linus Walleij:
Nomadik changes for the v3.19 development series:
- Rearrange the DTS files to make a pure SoC-specific file and
a pure board file for S8815.
- Add the device tree for the NDK15 board.
- Update the defconfig and configure in the STMPE expander by
default on the Nomadik.
* tag 'nomadik-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: nomadik: configure in STMPE support
ARM: update Nomadik config
ARM: nomadik: device tree for NHK15 board
ARM: nomadik: push ethernet down to board
ARM: nomadik: set up MCDATDIR2
ARM: nomadik: move GPIO I2C to S8815 board file
ARM: nomadik: disable chrystals in top level board files
ARM: nomadik: move MMC/SD card detect GPIO to board DTS
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Ux500 core changes for v3.19" from Linus Walleij:
"please pull in these Ux500 core changes for this kernel development
cycle: mainly a generic power domain implementation from Ulf Hansson
that needs to get queued up in -next and tested."
Generic power domains for the Ux500
* tag 'ux500-core-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: Add i2c devices to the VAPE PM domain
ARM: ux500: Add spi and ssp devices to the VAPE PM domain
ARM: ux500: Add sdi devices to the VAPE PM domain
ARM: ux500: Add DT node for ux500 PM domains
ARM: ux500: Enable Kconfig for the generic PM domain
ARM: ux500: Initial support for PM domains
dt: bindings: ux500: Add header for PM domains specifiers
dt: bindings: ux500: Add documentation for PM domains
ARM: u300: Convert pr_warning to pr_warn
Merge "ARM: berlin: DT changes for v3.19 (round 1)" from Sebastian Hesselbarth:
"This is Berlin DT changes for v3.19 and contains those patches that missed
the v3.18 merge window plus corresponding patches to catch-up with Antoine's
BG2Q improvements for BG2 and BG2CD. We now have working SDHCI and Ethernet
on all SoCs (well, BG2CD has HDMI HEC only), SATA PHY support for BG2 is still
pending."
Berlin DT changes for v3.19 (round 1)
- AHCI and SATA PHY nodes for BG2Q
- Reset controller binding docs
- Ethernet nodes for BG2, BG2CD
- SDHCI nodes for BG2, BG2CD
- Corresponding board changes to enable AHCI, Ethernet, SDHCI
* tag 'berlin-dt-3.19-1' of git://git.infradead.org/users/hesselba/linux-berlin:
ARM: dts: berlin: Enable eMMC on Sony NSZ-GS7
ARM: dts: berlin: Enable WiFi on Google Chromecast
ARM: dts: berlin: Add SDHCI controller nodes to BG2/BG2CD
ARM: dts: berlin: Enable ethernet on Sony NSZ-GS7
ARM: dts: berlin: Add phy-connection-type to BG2Q Ethernet
ARM: dts: berlin: Add BG2CD ethernet DT nodes
ARM: dts: berlin: Add BG2 ethernet DT nodes
ARM: dts: berlin: Add GPIO leds to Google Chromecast
ARM: dts: berlin: enable timer 1 for sched_clock
ARM: dts: berlin: add a required reset property in the chip controller node
Documentation: bindings: add reset bindings docs for Marvell Berlin SoCs
ARM: dts: berlin: enable the eSATA interface on the BG2Q DMP
ARM: dts: berlin: add the AHCI node for the BG2Q
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Broadcom Cygnus SoC Device Tree changes" from Florian Fianelli:
This patchset contains initial support for Broadcom's Cygnus SoC based on our
iProc architecture. Initial support is minimal and includes just the mach
platform code, clock driver, and a basic device tree configuration. Peripheral
drivers will be submitted soon, as will device tree configurations for other
Cygnus board variants.
These are the Device Tree changes
* tag 'arm-soc/for-3.18/cygnus-dts-v9' of http://github.com/brcm/linux:
ARM: dts: Enable Broadcom Cygnus SoC
dt-bindings: Document Broadcom Cygnus SoC and clocks
Signed-off-by: Olof Johansson <olof@lixom.net>
Add equivalent attributes to those provided in the platform data
for use when RX DMA is enabled.
Signed-off-by: Andrew Jackson <Andrew.Jackson@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Exynos7 I2S controller has no internal dma, supports more
no. of root clock sampling frequencies and has more no.of Rx
fifos to support 7.1CH recording in TDM mode. Due to more no.
of root clock frequency values some of the bit offsets got
shifted up by one. Also I2S1 on previous Samsung platforms
uses v3 dai type but on Exynos7 it is upgraded to v5 with
slightly modified register offsets for supporting more no.of
RFS values. Due to the above changes, the driver has to be
modified to handle all versions of I2S controller. For this
I introduced a new structure to hold modified bit offsets and
masks which is passed as dai data.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
The Hitachi TX23D38VM0CAA is a 9" WVGA TFT LCD panel and can be
supported by the simple-panel driver.
This panel is connected via LVDS and uses the data enable signal for
timing. Since HSYNC/VSYNC are ignored, the split between sync length and
porches is arbitrary, as long as the complete horizontal blanking interval
is 256 clocks, and the vertical blanking interval is 45 lines.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Innolux G121I1-L01 is a 12.1" TFT LCD panel and can be supported by
the simple-panel driver.
This panel is connected via LVDS and uses the data enable signal for
timing. Since HSYNC/VSYNC are ignored, the split between sync length and
porches is arbitrary, as long as the complete horizontal blanking interval
is 160 clocks, and the vertical blanking interval is 24 lines.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The AUO B116XW03 is a 11.6" HD TFT LCD panel connecting to a LVDS
interface and with an integrated LED backlight unit.
This panel is used on the Samsung Chromebook(XE303C12).
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
[treding@nvidia.com: add missing .bpc field]
Signed-off-by: Thierry Reding <treding@nvidia.com>
This patch adds support for the HannStar Display Corp. HSD070PWW1 7.0"
WXGA TFT LCD panel to the simple-panel driver. The binding documentation
is included.
This panel is connected via LVDS and uses the data enable signal for
timing. Since HSYNC/VSYNC are ignored, the split between sync length and
porches is arbitrary, as long as the complete horizontal blanking interval
is 160 clocks, and the vertical blanking interval is 23 lines.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This squashes a checkpatch warning on my new bcm3384 dts submission.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Dedicated CTS and RTS pins are unusable together with a lot of other
peripherals because they share the same line. Pinctrl is limited.
Moreover, the AUART controller doesn't handle DTR/DSR/DCD/RI signals,
so we have to control them via GPIO.
This patch permits to use GPIOs to control the CTS/RTS/DTR/DSR/DCD/RI
signals.
Signed-off-by: Janusz Uzycki <j.uzycki@elproma.com.pl>
Reviewed-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This patch provides support for interrupts that are generated by the
Tx/Rx DMA channel pairs of the device. This allows for Tx and Rx
processing to run across multiple processsors.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
If there is no PMECC lookup table stored in ROM, or lookup table offset is
not specified, PMECC driver should build it in DDR by itself.
That make the PMECC driver work for some board which doesn't have PMECC
lookup table in ROM.
The PMECC use the BCH algorithm, so based on the build_gf_tables()
function in lib/bch.c, we can build the Galois Field lookup table.
For more information can refer to section 5.4 of PMECC controller
application note:
http://www.atmel.com/images/doc11127.pdf
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Makes it possible to define a rockchip,pmu phandle in the cpus node directly
referencing the pmu syscon instead of searching for specific compatible.
The old way of finding the pmu stays of course available.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Jonathan writes:
First round of new drivers, features and cleanups for IIO in the 3.19 cycle.
New drivers / supported parts
* rockchip - rk3066-tsadc variant
* si7020 humidity and temperature sensor
* mcp320x - add mcp3001, mcp3002, mcp3004, mcp3008, mcp3201, mcp3202
* bmp280 pressure and temperature sensor
* Qualcomm SPMI PMIC current ADC driver
* Exynos_adc - support exynos7
New features
* vf610-adc - add temperature sensor support
* Documentation of current attributes, scaled pressure, offset and
scaled humidity, RGBC intensity gain factor and scale applied to
differential voltage channels.
* Bring iio_event_monitor up to date with newer modifiers.
* Add of_xlate function to allow for complex channel mappings from the
device tree.
* Add -g parameter to generic_buffer example to allow for devices with
directly fed (no trigger) buffers.
* Move exynos driver over to syscon for PMU register access.
Cleanups, fixes for new drivers
* lis3l02dq drop an unneeded else.
* st sensors - renam st_sensors to st_sensor_settings (for clarity)
* st sensors - drop an unused parameter from all the probe utility
functions.
* vf610 better error handling and tidy up.
* si7020 - cleanups following merge
* as3935 - drop some unnecessary semicolons.
* bmp280 - fix the pressure calculation.
The ADC on exynos7 is quite similar to ADCv2. The differences are as
follows:
- exynos7-adc has 8 input channels (as against 10 in ADCv2).
- exynos7 does not include an ADC PHY control register.
- Some ADC_CON2 register bits being used in ADCv2 are listed as
reserved in exynos7-adc. This results in a different init_hw
function for exynos7.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Expand the description of the 'gpios' property in the GPIO assisted
NAND flash binding, to explicitly list the required GPIO pin references
and their order.
Update the example section to individually bracket the GPIO references,
and capitalize the signal names for improved readability.
Signed-off-by: Gerhard Sittig <gsi@denx.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Merge "Renesas ARM Based SoC DT Clocksource Updates for v3.19" from Simon
Horman:
* sh_mtu2: Drop incorrect SoC family name
* sh_tmu: Document r8a7778 and r8a7740 bindings
* tag 'renesas-dt-clocksource-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
clocksource: sh_mtu2: Drop incorrect SoC family name
clocksource: sh_tmu: Document r8a7778 binding
clocksource: sh_tmu: Document R-Mobile r8a7740 binding
Signed-off-by: Olof Johansson <olof@lixom.net>
In addtion expand the table to handle other values of sysclk. Instead
of making the table 3D, expand it to a more descriptive struct. The
divisors are specified in Table 19 of the 98090 data sheet version
0p94.
The dmic frequency was previously assumed. Instead make it explicit
and configurable through device tree. This now handles independently
set pclk and dmic frequency.
Based on downstream work by Ralph Birt.
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Pull thermal fixes from Eduardo Valentin:
"Specifics:
- a few code fixes improving the Exynos code base. They remove dead
and unreachable code. No functional changes here
- in Exynos code base, fixes regarding the right usage of features
(TRIMINFO and TRIMRELOAD)
- documentation of RCAR thermal
- fix in the of-thermal, regarding the proper usage of of-APIs
- fixes on thermal-core, removal of unreachable code"
[ Eduardo is sending the thermal fixes on behalf of Rui Zhang this time.
Rui is currently unable to send pull requests due to troubles with his
machine and he's currently in a business trip ]
* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal:
Thermal:Remove usless if(!result) before return tz
thermal: exynos: fix IRQ clearing on TMU initialization
thermal: fix multiple disbalanced device node counters
thermal: rcar: Add binding docs for new R-Car Gen2 SoCs
thermal: exynos: Add support for TRIM_RELOAD feature at Exynos3250
thermal: exynos: Add support for many TRIMINFO_CTRL registers
thermal: samsung: Exynos5260 and Exynos5420 should not use TRIM_RELOAD flag
thermal: exynos: remove identical values from exynos*_tmu_registers structures
thermal: exynos: remove redundant pdata checks from exynos_tmu_control()
thermal: exynos: cache non_hw_trigger_levels in pdata
thermal: exynos: simplify temp_to_code() and code_to_temp()
thermal: exynos: remove redundant threshold_code checks from exynos_tmu_initialize()
thermal: exynos: remove redundant pdata checks from exynos_tmu_initialize()
thermal: exynos: remove dead code for HW_MODE calibration
thermal: exynos: remove unused struct exynos_tmu_registers entries
In order to describe a single slave device that has no chip select line
the 'num-chipselects' property has to be <0> and the 'cs-gpios' property
doesn't need to be set.
Signed-off-by: Torsten Fleischer <torfl6749@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
