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David Daney
24d4e7f642 MIPS: OCTEON: Add semaphore to serialize bootbus accesses. 
Some hardware blocks attached to the OCTEON bootbus run asynchronously
to accesses from the CPUs.  These include MMC/SD host, CF(when using
DMA), and NAND controller.  A bus error, or corrupt data may occur if
a CPU is trying to access a bootbus connected device at the same time
the bus is running asynchronous operations.

To work around these problems we add this semaphore that must be
acquired before initiating bootbus activity.  Subsequent patches will
add users for this.

Signed-off-by: David Daney <david.daney@cavium.com>
[aleksey.makarov@auriga.com: combine the patches]
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9459/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:42 +02:00
Kevin Cernekee
8945e37e10 MIPS: BMIPS: Add DTS files for several platforms 
Most of the supported chips use legacy (non-DT) bootloaders, so they will
need to select an appropriate builtin DTB at compile time until the
bootloader is updated.  Provide suitable DTS files, and a means to compile
one of them into the kernel image.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
Cc: f.fainelli@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8858/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:42 +02:00
Kevin Cernekee
81a07b4abe MIPS: BMIPS: Update DT bindings to reflect new SoC support 
Add an entry for each supported Broadcom SoC.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
Cc: f.fainelli@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8857/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:42 +02:00
Kevin Cernekee
cd586ebc32 MIPS: BMIPS: Refresh BCM3384 DTS files 
The DT bindings for this platform have changed as the bootloader and
product requirements evolved.  In particular, there are both
Linux-on-Zephyr and Linux-on-Viper configurations.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8856/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:42 +02:00
Kevin Cernekee
60b858f225 MIPS: BMIPS: Enable additional peripheral and CPU support in defconfig 
Also, add an LE defconfig for set-top box (BCM7xxx).  This will allow the
BMIPS kernel to run on several non-BCM3384 platforms.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
Cc: f.fainelli@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8855/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:41 +02:00
Kevin Cernekee
66cc8ff3eb MIPS: BMIPS: Use a non-default FIXADDR_TOP setting 
This will be required to support BMIPS3300 platforms.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8854/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:41 +02:00
Kevin Cernekee
e5a6fcc058 MIPS: BMIPS: Delete the irqchip driver from irq.c 
BCM3384/BCM63xx can use the common drivers/irqchip/irq-bcm7120-l2.c for
this purpose; BCM7xxx will use drivers/irqchip/irq-bcm7038-l1.c.  We no
longer need this code under arch/mips.

[ralf@linux-mips.org: Fix conflicts.]

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8853/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:41 +02:00
Kevin Cernekee
4b049a6b27 MIPS: BMIPS: Add quirks for several Broadcom platforms 
A couple of chips require special handling in order to make SMP secondary
boot and/or exception vectors work correctly.  Take care of these in
setup.c.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8852/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:40 +02:00
Kevin Cernekee
c4b2570917 MIPS: BMIPS: Remove bogus bus name 
There is no "bcm3384" bus so let's just remove it to avoid confusion.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8851/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:39 +02:00
Kevin Cernekee
1ada656f67 MIPS: BMIPS: Rewrite DMA code to use "dma-ranges" property 
This is a more standardized way of handling DMA remapping, and it is
suitable for the memory map found on BCM3384.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8850/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:39 +02:00
Kevin Cernekee
9c24ce29b2 MIPS: BMIPS: Document the firmware->kernel DTB interface 
Add a new section covering the Generic BMIPS machine type.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8849/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:38 +02:00
Kevin Cernekee
5432eeb6fa MIPS: Reorder MIPS_L1_CACHE_SHIFT priorities 
Enabling support for more than one BMIPS CPU in the same build may
result in different L1_CACHE_SHIFT values, e.g.

    CPU_BMIPS5000 selects MIPS_L1_CACHE_SHIFT_7
    CPU_BMIPS4380 selects MIPS_L1_CACHE_SHIFT_6
    anything else defaults to MIPS_L1_CACHE_SHIFT_5

Ensure that if more than one MIPS_L1_CACHE_SHIFT_x option is selected,
Kconfig sets CONFIG_MIPS_L1_CACHE_SHIFT to the highest value.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8847/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:38 +02:00
Kevin Cernekee
9127dc478c MIPS: Let __dt_register_buses accept a single bus type 
Some machines only have one bus type to register (e.g. "simple-bus").

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8845/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:38 +02:00
Kevin Cernekee
5f7f0317ed IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllers 
This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
it has the following characteristics:

 - 64 to 160+ level IRQs
 - Atomic set/clear registers
 - Reasonably predictable register layout (N status words, then N
   mask status words, then N mask set words, then N mask clear words)
 - SMP affinity supported on most systems
 - Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3

This driver registers one IRQ domain and one IRQ chip to cover all
instances of the block.  Up to 4 instances of the block may appear, as
it supports 4-way IRQ affinity on BCM7435.

The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC
is used instead.  So this driver is primarily intended for MIPS STB chips.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8844/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:37 +02:00
Kevin Cernekee
7b7230e70e IRQCHIP: bcm7120-l2: Add support for BCM3380-style controllers 
These controllers support multiple enable/status pairs (64+ IRQs),
can put the enable/status words at different offsets, and do not
support multiple parent IRQs.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8843/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:37 +02:00
Kevin Cernekee
ca40f1b23d IRQCHIP: bcm7120-l2: Split STB-specific logic into its own function 
The BCM7xxx instances of this block (listed in the register manual as
simply "IRQ0") all have the following items in common:

 - brcm,int-map-mask: for routing different bits in the L2 to different
   parent IRQs

 - brcm,int-fwd-mask: for hardwiring certain IRQs to bypass the L2 and
   use dedicated L1 lines

 - one enable/status pair (32 bits only)

Much of the driver code can be shared with BCM3380-style controllers, but
in order to do this cleanly, let's split out the BCM7xxx-specific logic
first.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8842/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:37 +02:00
Kevin Cernekee
5b5468cf1f IRQCHIP: bcm7120-l2: Refactor driver for arbitrary IRQEN/IRQSTAT offsets 
Currently the driver assumes that REG_BASE+0x00 is the IRQ enable mask,
and REG_BASE+0x04 is the IRQ status mask.  This is true on BCM3384 and
BCM7xxx, but it is not true for some of the controllers found on BCM63xx
chips.  So we will change a couple of key assumptions:

 - Don't assume that both the IRQEN and IRQSTAT registers will be
   covered by a single ioremap() operation.

 - Don't assume any particular ordering (IRQSTAT might show up before
   IRQEN on some chips).

 - For an L2 controller with >=64 IRQs, don't assume that every
   IRQEN/IRQSTAT pair will use the same register spacing.

This patch changes the "plumbing" but doesn't yet provide a way for users
to instantiate a controller with arbitrary IRQEN/IRQSTAT offsets.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8841/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:37 +02:00
Brian Norris
c9ae71e0f7 IRQCHIP: brcmstb-l2: don't clear wakeable interrupts at init time 
Wakeable interrupts might be pending at boot/init time, because wakeup
interrupts might have triggered a resume from S5. So don't clear such
wakeups.

This means that any driver which requests a wakeable interrupt bit
should be prepared to handle an interrupt as soon as they call
request_irq(). (This is technically already the correct development
practice, but some drivers probably expect not to receive interrupts
until they have performed some I/O.)

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8840/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:36 +02:00
Kevin Cernekee
7e229fa07d IRQCHIP: Update docs regarding irq_domain_add_tree() 
Several drivers now use this API, including the ARM GIC driver, so remove
the outdated comment.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8839/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:35 +02:00
Kevin Cernekee
5f2d44591f MIPS: bcm3384: Rename "bcm3384" target to "bmips" 
This platform is configured primarily through device tree, and we can
reuse the same code to support a bunch of other chips.  Change the name
to reflect this.

[ralf@linux-mips.org: Fix conflicts with other patches.]

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8838/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:35 +02:00
Andrew Bresticker
eb2236ea58 MIPS: Add dtbs_install target 
Add the dtbs_install Makefile target to install the dtb files into
$INSTALL_DTBS_PATH.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8836/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:34 +02:00
Andrew Bresticker
8c0b9ee866 MIPS: Move device-trees into vendor sub-directories 
Move the MIPS device-trees into the appropriate vendor sub-directories.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8835/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:34 +02:00
Deng-Cheng Zhu
ec9ddad3c6 MIPS: Add support for fine granularity task level IRQ time accounting 
With sched_clock being ready, it makes sense to add the option of IRQ time
accounting -- When we have a fast enough sched_clock, IRQ time accounting
will be enabled (see sched_clock_register).

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9489/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:34 +02:00
Deng-Cheng Zhu
262f1c9291 MIPS: csrc-sb1250: Implement read_sched_clock 
Use sb1250 hpt for sched_clock source. This implementation will give high
resolution cputime accounting.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9488/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:33 +02:00
Deng-Cheng Zhu
0dc886aba2 MIPS: csrc-sb1250: Remove FSF mail address from GPL notice 
This is to make checkpatch.pl happy for the next patch. It would otherwise
say --

ERROR: Do not include the paragraph about writing to the Free Software
Foundation's mailing address from the sample GPL notice. The FSF has
changed addresses in the past, and may do so again. Linux already includes
a copy of the GPL.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9487/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:33 +02:00
Deng-Cheng Zhu
02710fc851 MIPS: csrc-sb1250: Extract hpt cycle acquisition from sb1250_hpt_read 
This is to prepare for the upcoming read_sched_clock implementation, which
will also need to get cycles from the high precision timer.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9486/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:33 +02:00
Deng-Cheng Zhu
944081ac53 MIPS: jz4740: Implement read_sched_clock 
Use jz4740 timer counter for sched_clock source. This implementation will
give high resolution cputime accounting.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9485/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:31 +02:00
Deng-Cheng Zhu
a6071af914 MIPS: cevt-txx9: Implement read_sched_clock 
Use txx9 up-counter for sched_clock source. This implementation will give
high resolution cputime accounting.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9484/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:30 +02:00
Deng-Cheng Zhu
c41cef3653 MIPS: sgi-ip27: Implement read_sched_clock 
Use ip27 hub real time counter for sched_clock source. This implementation
will give high resolution cputime accounting.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9483/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:29 +02:00
Deng-Cheng Zhu
7cb24b7003 MIPS: csrc-ioasic: Implement read_sched_clock 
Use DEC I/O ASIC's free-running counter for sched_clock source. This
implementation will give high resolution cputime accounting.

Acked-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9482/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:28 +02:00
Deng-Cheng Zhu
317adb12e5 MIPS: csrc-ioasic: Remove FSF mail address from GPL notice 
This is to make checkpatch.pl happy for the next patch. It would otherwise
say --

ERROR: Do not include the paragraph about writing to the Free Software
Foundation's mailing address from the sample GPL notice. The FSF has
changed addresses in the past, and may do so again. Linux already includes
a copy of the GPL.

Acked-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9481/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:28 +02:00
Deng-Cheng Zhu
27acdea8fe MIPS: csrc-bcm1480: Implement read_sched_clock 
Use the ZBbus cycle counter for sched_clock source. This implementation
will give high resolution cputime accounting.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9480/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:27 +02:00
Deng-Cheng Zhu
788049e2d5 MIPS: csrc-bcm1480: Remove FSF mail address from GPL notice 
This is to make checkpatch.pl happy for the next patch. It would otherwise
say --

ERROR: Do not include the paragraph about writing to the Free Software
Foundation's mailing address from the sample GPL notice. The FSF has
changed addresses in the past, and may do so again. Linux already includes
a copy of the GPL.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9479/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:27 +02:00
Deng-Cheng Zhu
e9cef549c3 MIPS: csrc-r4k: Implement read_sched_clock 
Use c0 count register for sched_clock source. This implementation will give
high resolution cputime accounting.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9478/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:27 +02:00
Deng-Cheng Zhu
929de4cc97 MIPS: Add sched_clock support 
This will provide sched_clock interface to implement individual
read_sched_clock(). Not for CAVIUM_OCTEON_SOC as it defines its own
sched_clock() directly (not using the sched_clock_register interface).

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9477/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:26 +02:00
Deng-Cheng Zhu
ff37015b6d CLOCKSOURCE: versatile: Add PLAT_VERSATILE dependency 
GENERIC_SCHED_CLOCK can be selected by architectures other than ARM. The
current dependencies of CLKSRC_VERSATILE make it possible that other
architectures will have CLKSRC_VERSATILE available in configuration once
they select GENERIC_SCHED_CLOCK, whereas this clock source should be solely
available to ARM in reality.

This patch adds one more dependency to CLKSRC_VERSATILE to fix the issue.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Reported-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: LKML <linux-kernel@vger.kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9476/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:26 +02:00
Deng-Cheng Zhu
bb877e96be MIPS: Add support for full dynticks CPU time accounting 
With the correct cmpxchg64 on 32-bit platforms, we can now add the config
HAVE_VIRT_CPU_ACCOUNTING_GEN into arch/mips/Kconfig.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9475/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:25 +02:00
Deng-Cheng Zhu
e2093c7b03 MIPS: Fall back to generic implementation of cmpxchg64 on 32-bit platforms 
This is in preparation of adding HAVE_VIRT_CPU_ACCOUNTING_GEN support in
the next patch.

Without having cmpxchg64 to use the generic implementation, kernel linking
will complain:

kernel/built-in.o: In function `cputime_adjust':
cputime.c:(.text+0x33748): undefined reference to `__cmpxchg_called_with_bad_pointer'
cputime.c:(.text+0x33810): undefined reference to `__cmpxchg_called_with_bad_pointer'

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9474/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:25 +02:00
Deng-Cheng Zhu
96685b1710 MIPS: Add SCHED_HRTICK support 
We have HIGH_RES_TIMERS to support SCHED_HRTICK. But SCHED_HRTICK is in
kernel/Kconfig.hz where HZ values unsuitable for MIPS are defined. So we
simply add this config in arch/mips/Kconfig as opposed to including the
whole kernel/Kconfig.hz.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9473/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:25 +02:00
David Daney
73569d87e2 MIPS: OCTEON: Enable little endian kernel. 
Now it is supported, so let people select it.

[ralf@linux-mips.org: Folded in fix for bogus CONFIG_ kconfig symbol
prefix.  Issue reported by Valentin Rothberg <valentinrothberg@gmail.com>.]

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Leonid Rosenboim <lrosenboim@caviumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9592/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:24 +02:00
David Daney
e7916357e7 MIPS: OCTEON: Add mach-cavium-octeon/mangle-port.h 
Needed for little-endian ioport access.
This fixes NOR flash in little-endian mode

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9591/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:24 +02:00
David Daney
534c158ea6 MIPS: Octeon: Handle bootloader structures in little-endian mode. 
Compensate for the differences in the layout of in-memory bootloader
information as seen from little-endian mode.

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9590/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-04-01 17:21:23 +02:00
Markos Chandras
be37a9900b MIPS: Malta: malta-time: Ensure GIC counter is running 
Start the GIC counter before we try to determine its frequency.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9596/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-03-31 12:04:13 +02:00
Markos Chandras
7d9cd1f518 CLOCKSOURCE: mips-gic-timer: Ensure GIC counter is running 
Start the GIC counter after configuring the clocksource since there
are no guarantees the counter will be running after a CPU reset.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9595/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-03-31 12:04:13 +02:00
Markos Chandras
8fa4b93067 IRQCHIP: irq-mips-gic: Add new functions to start/stop the GIC counter 
We add new functions to start and stop the GIC counter since there are no
guarantees the counter will be running after a CPU reset. The GIC counter
is stopped by setting the 29th bit on the GIC Config register and it is
started by clearing that bit.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9594/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-03-31 12:04:13 +02:00
James Hogan
c2d7ef51d7 ttyFDC: Implement KGDB IO operations. 
Implement KGDB IO operations for MIPS Fast Debug Channel (FDC). This can
be enabled via Kconfig, which also allows the channel number to be
chosen.

The magic sysrq hack is implemented in the TTY driver, detecting just ^C
for the KGDB channel, and ^O followed by a letter for the FDC console
channel.

The KGDB operations are reasonably efficient thanks to the flush
callback, with a 4 byte buffer being used in both directions to allow up
to 4 bytes to be encoded per FDC word. Reading of data for KGDB will
discard any data received on other channels, which clearly isn't ideal,
but given that there is a single FIFO shared between channels we can't
do much better.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jslaby@suse.cz>
Cc: Jason Wessel <jason.wessel@windriver.com>
Cc: linux-mips@linux-mips.org
Cc: kgdb-bugreport@lists.sourceforge.net
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9147/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-03-31 12:04:13 +02:00
James Hogan
e934945db7 MIPS, ttyFDC: Add early FDC console support 
Add support for early console of MIPS Fast Debug Channel (FDC) on
channel 1 with a call very early from the MIPS setup_arch().

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jslaby@suse.cz>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9145/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-03-31 12:04:12 +02:00
James Hogan
4cebec609a TTY: Add MIPS EJTAG Fast Debug Channel TTY driver 
Add TTY driver and consoles for the MIPS EJTAG Fast Debug Channel (FDC),
which is found on the per-CPU MIPS Common Device Mapped Memory (CDMM)
bus.

The FDC is a per-CPU device which is used to communicate with an EJTAG
probe. RX and TX FIFOs exist, containing 32-bits of data and 4-bit
channel numbers. 16 general data streams are implemented on this for TTY
and console use by encoding up to 4 bytes on each 32-bit FDC word.

The TTY devices are named e.g. /dev/ttyFDC3c2 for channel 2 of the FDC
attached to logical CPU 3.

These can be used for getting the kernel log, a login prompt, or as a
GDB remote transport, all over EJTAG and without needing a serial port.

It can have an interrupt to notify of when incoming data is available in
the RX FIFO or when the TX FIFO is no longer full. The detection of this
interrupt occurs in architecture / platform code, but it may be shared
with the timer and/or performance counter interrupt.

Due to the per-CPU nature of the hardware, all outgoing TTY data is
written out from a kthread which is pinned to the appropriate CPU.

The console is not bound to a specific CPU, so output will appear on the
chosen channel on whichever CPU the code is executing on. Enable with
e.g. console=fdc1 in kernel arguments. /dev/console is bound to the same
channel on the boot CPU's FDC if it exists.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jslaby@suse.cz>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9146/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-03-31 12:04:12 +02:00
James Hogan
e38df288a9 MIPS: idle: Workaround wait + FDC problems 
On certain cores (namely proAptiv and P5600) incoming data via a Fast
Debug Channel (FDC) while the core is blocked on a wait instruction will
cause the wait not to wake up even when another interrupt is received.
This makes an idle target stop as soon as you send FDC data to it, until
the debug probe interrupts it and restarts the wait instruction.

This is worked around by avoiding using r4k_wait on these cores if
CONFIG_MIPS_EJTAG_FDC_TTY is enabled (which would imply the user intends
to use the FDC).

[ralf@linux-mips.org: Fix conflict.]

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9144/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-03-31 12:04:12 +02:00
James Hogan
602e8a345a MIPS: Malta: Implement get_c0_fdc_int() 
Implement the weak get_c0_fdc_int() function for Malta. The Fast Debug
Channel (FDC) interrupt is obtained mainly depending on whether a GIC is
present. Vectored external interrupt mode isn't yet supported.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9143/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-03-31 12:04:12 +02:00