Claudiu Beznea
91f3bf0d53
clk: at91: sama7g5: register cpu clock
...
Register CPU clock as being the master clock prescaler. This would
be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
frequencies supported by SAMA7G5 could be directly received from
CPUPLL + master clock prescaler and the extra divider would do no work in
case it would be enabled.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com >
Link: https://lore.kernel.org/r/1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-12-19 11:50:56 -08:00
Claudiu Beznea
7a110b9107
clk: at91: clk-master: re-factor master clock
...
Re-factor master clock driver by splitting it into 2 clocks: prescaller
and divider clocks. Based on registered clock flags the prescaler's rate
could be changed at runtime. This is necessary for platforms supporting
DVFS (e.g. SAMA7G5) where master clock could be changed at run-time.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com >
Link: https://lore.kernel.org/r/1605800597-16720-11-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-12-19 11:50:56 -08:00
Claudiu Beznea
120d5d8b46
clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz
...
Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher
than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at
1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com >
Link: https://lore.kernel.org/r/1605800597-16720-10-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-12-19 11:50:56 -08:00
Claudiu Beznea
f803858af8
clk: at91: sama7g5: decrease lower limit for MCK0 rate
...
On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and
CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is
also changed by DVFS to avoid over/under clocking of MCK0 consumers.
The lower limit is changed to be able to set MCK0 accordingly by
DVFS.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com >
Link: https://lore.kernel.org/r/1605800597-16720-9-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-12-19 11:50:56 -08:00
Claudiu Beznea
4011f03ee4
clk: at91: sama7g5: remove mck0 from parent list of other clocks
...
MCK0 is changed at runtime by DVFS. Due to this, since not all IPs
are glitch free aware at MCK0 changes, remove MCK0 from parent list
of other clocks (e.g. generic clock, programmable/system clock, MCKX).
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com >
Link: https://lore.kernel.org/r/1605800597-16720-8-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-12-19 11:50:56 -08:00
Claudiu Beznea
8dc4af8bef
clk: at91: clk-sam9x60-pll: allow runtime changes for pll
...
Allow runtime frequency changes for PLLs registered with proper flags.
This is necessary for CPU PLL on SAMA7G5 which is used by DVFS.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com >
Link: https://lore.kernel.org/r/1605800597-16720-7-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-12-19 11:50:55 -08:00
Eugen Hristev
0bb4623f13
clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
...
This SoC has the 5th divisor for the mck0 master clock.
Adapt the characteristics accordingly.
Reported-by: Mihai Sain <mihai.sain@microchip.com >
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com >
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com >
Link: https://lore.kernel.org/r/1605800597-16720-6-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-12-19 11:50:55 -08:00
Eugen Hristev
83d0028773
clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT
...
Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock
from phandle in DT.
Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com >
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com >
[claudiu.beznea@microchip.com: adapt commit message, add CPU PLL]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-4-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-12-19 11:50:55 -08:00
Eugen Hristev
3d86ee17d4
dt-bindings: clock: at91: add sama7g5 pll defines
...
Add SAMA7G5 specific PLL defines to be referenced in a phandle as a
PMC_TYPE_CORE clock.
Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com >
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com >
[claudiu.beznea@microchip.com: adapt comit message, adapt sama7g5.c]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-3-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-12-19 11:50:55 -08:00
Claudiu Beznea
91274497c7
clk: at91: sama7g5: fix compilation error
...
pmc_data_allocate() has been changed. pmc_data_free() was removed.
Adapt the code taking this into consideration. With this the programmable
clocks were also saved in sama7g5_pmc so that they could be later
referenced.
Fixes: cb783bbbcfclaudiu.beznea@microchip.com >
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com >
Tested-by: Tudor Ambarus <tudor.ambarus@microchip.com >
Link: https://lore.kernel.org/r/1605800597-16720-2-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-12-19 11:50:55 -08:00
Claudiu Beznea
cb783bbbcf
clk: at91: sama7g5: add clock support for sama7g5
...
Add clock support for SAMA7G5.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com >
Link: https://lore.kernel.org/r/1595403506-8209-19-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-07-24 02:19:09 -07:00
